MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 50

• Manufacturer Part Number: MPC8309VMAHFCA
• Description: 417/333/233 MP Std Tmp
• Manufacturer: Freescale Semiconductor

Specifications of MPC8309VMAHFCA

• Processor Series: MPC8309
• Core: e300c3
• Data Bus Width: 32 bit
• Data Ram Size: 512 MB
• Interface Type: USB, CAN, UART, PCI
• Maximum Clock Frequency: 417 MHz
• Number Of Programmable I/os: 56
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 105 C
• Processor To Be Evaluated: MPC8309
• Supply Current (max): 5 uA
• Lead Free Status / Rohs Status: Details

JTAG
The following figure provides the AC test load for TDO and the boundary-scan outputs of the MPC8309.
The following figure provides the JTAG clock input timing diagram.
The following figure provides the TRST timing diagram.
50
At recommended operating conditions (see
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
The output timings are measured at the pins. All output timings assume a purely resistive 50-load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
inputs and t
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Table 54. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)
(first two letters of functional block)(reference)(state)(signal)(state)
External Clock
TRST
Parameter
JTAG
Output
Figure 39. AC Test Load for the JTAG Interface
JTG
Figure 40. JTAG Clock Input Timing Diagram
Boundary-scan data
Boundary-scan data
Table
VM
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
t
JTKHKL
Figure 41. TRST Timing Diagram
2).
VM
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
JTDXKH
TCLK
Z
t
JTG
TCLK
0
TDO
TDO
= 50 
.
VM
.
symbolizes JTAG timing (JT) with respect to the time data input signals
t
TRST
Symbol
t
t
t
t
JTKLOX
JTKLDX
JTKLDZ
JTKLOZ
VM
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
2
R
L
VM
= 50 
TCLK
Min
t
JTGR
2
2
2
2
to the midpoint of the signal in question.
OV
JTDVKH
DD
Max
t
JTGF
19
/2
—
—
9
1
(continued)
symbolizes JTAG device
Freescale Semiconductor
JTG
clock reference (K)
Unit
Figure
ns
ns
39).
Notes
5, 6
5
6
for