EP3C25F256C7N Altera, EP3C25F256C7N Datasheet - Page 229

• Manufacturer Part Number: EP3C25F256C7N
• Description: IC CYCLONE III FPGA 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F256C7N

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 156
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 156
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: Q4433068

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 2 of 4)
© December 2009
CONF_DONE
nCE
nCEO
FLASH_nCE,
nCSO
Pin Name
Altera Corporation
option is
on. I/O if
option is
Mode
N/A if
User
N/A
N/A
off.
I/O
Configuration
AS, AP
Scheme
All
All
All
(1)
Bidirectional
Output open
open-drain
Pin Type
Output
Input
drain
■
■
Driving CONF_DONE low after configuration and
initialization does not affect the configured device. Do not
connect bus holds or ADC to the CONF_DONE pin.
Active-low chip enable. The nCE pin activates the Cyclone III
device family with a low signal to allow configuration. The
nCE pin must be held low during configuration, initialization,
and user-mode. In a single-device configuration, it must be
tied low. In a multi-device configuration, nCE of the first
device is tied low while its nCEO pin is connected to the nCE
pin of the next device in the chain. The nCE pin must also be
held low for successful JTAG programming of the device.
Output that drives low when configuration is complete. In a
single-device configuration, you can leave this pin floating or
use it as a user I/O pin after configuration. In a multi-device
configuration, this pin feeds the nCE pin of the next device.
The nCEO of the last device in the chain is left floating or is
used as a user I/O pin after configuration.
If you use the nCEO pin to feed the nCE pin of the next
device, use an external 10-kΩ pull-up resistor to pull the
nCEO pin high to the V
internal weak pull-up resistor.
If you use the nCEO pin as a user I/O pin after configuration,
set the state of the pin on the Dual-Purpose Pin settings.
Output control signal from the Cyclone III device family to the
serial configuration device in AS mode that enables the
configuration device. This pin functions as the nCSO pin in
AS mode and the FLASH_NCE pin in AP mode.
Output control signal from the Cyclone III device to the
parallel flash in AP mode that enables the flash. Connects to
the CE# pin on the Numonyx P30 or P33 flash.
This pin has an internal pull-up resistor that is always active.
Status output. The target Cyclone III device family drives
the CONF_DONE pin low before and during configuration.
After all configuration data is received without error and
the initialization cycle starts, the target device releases
CONF_DONE.
Status input. After all data is received and CONF_DONE
goes high, the target device initializes and enters user
mode. The CONF_DONE pin must have an external 10-kΩ
pull-up resistor in order for the device to initialize.
CC IO
Description
voltage of its I/O bank to help the
Cyclone III Device Handbook, Volume 1
(1)
9–69