EP3C25F256C7N Altera, EP3C25F256C7N Datasheet - Page 83

• Manufacturer Part Number: EP3C25F256C7N
• Description: IC CYCLONE III FPGA 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F256C7N

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 156
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 156
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: Q4433068

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Hardware Features
© December 2009
Altera Corporation
There are two ways to use the clock switchover feature:
■
■
Figure 5–15
automatic loss of clock detection. Here, the inclk0 signal remains low. After the
inclk0 signal remains low for approximately two clock cycles, the clock-sense
circuitry drives the clkbad[0] signal high. Also, because the reference clock signal is
not toggling, the switchover state machine controls the multiplexer through the
clksw signal to switch to inclk1.
Figure 5–15. Automatic Switchover Upon Clock Loss Detection
Note to
(1) Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this
Use the switchover circuitry for switching from inclk0 to inclk1 running at the
same frequency. For example, in applications that require a redundant clock with
the same frequency as the reference clock, the switchover state machine generates
a signal that controls the multiplexer select input shown in
case, inclk1 becomes the reference clock for the PLL. This automatic switchover
can switch back and forth between the inclk0 and inclk1 clocks any number of
times, when one of the two clocks fails and the other clock is available.
Use the clkswitch input for user- or system-controlled switch conditions. This is
possible for same-frequency switchover or to switch between inputs of different
frequencies. For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must
control the switchover because the automatic clock-sense circuitry cannot monitor
primary and secondary clock frequencies with a frequency difference of more than
20%. This feature is useful when clock sources can originate from multiple cards
on the backplane, requiring a system-controlled switchover between frequencies
of operation. Choose the secondary clock frequency so the VCO operates in the
recommended frequency range. Also, set the M, N, and C counters accordingly to
keep the VCO operating frequency in the recommended range.
figure, switchover is enabled on the falling edge of inclk1.
Figure
5–15:
shows a waveform example of the switchover feature when using
activeclock
clkbad0
clkbad1
muxout
inclk0
inclk1
(1)
(Note 1)
Cyclone III Device Handbook, Volume 1
Figure
5–14. In this
5–19