XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 100

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
GWE_cycle
GTS_cycle
LCK_cycle
DonePin
DriveDone
DonePipe
ProgPin
TckPin
TdiPin
Option Name
R
Pins/Function
JTAG TCK pin
shift registers,
Configuration
Configuration
Configuration
JTAG TDI pin
PROG_B pin
All flip-flops,
LUT RAMs,
Block RAM,
All I/O pins,
and SRL16
DONE pin
DONE pin
DONE pin
Affected
Startup
Startup
DCMs,
1, 2, 3, 4,
1, 2, 3, 4,
0, 1, 2, 3,
Pulldown
Pulldown
( default )
Pullnone
Pullnone
Pullnone
Pullnone
NoWait
Values
Pullup
Pullup
Pullup
Pullup
4, 5, 6
Done
Done
Keep
Keep
5, 6
5 , 6
Yes
Yes
No
No
Selects the Configuration Startup phase that asserts the internal write-enable signal to
all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read
and write operations. See
Waits for the DONE pin input to go High before asserting the internal write-enable
signal to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and
write operations are enabled at this time.
Retains the current GWE_cycle setting for partial reconfiguration applications.
Selects the Configuration Startup phase that releases the internal three-state control,
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point. See
Waits for the DONE pin input to go High before releasing the internal three-state
control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive,
if so configured, after this point.
Retains the current GTS_cycle setting for partial reconfiguration applications.
The FPGA does not wait for selected DCMs to lock before completing configuration.
If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE,
the FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
Internally connects a pull-up resistor between DONE pin and VCCAUX. An external
330 Ω pull-up resistor to VCCAUX is still recommended.
No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to
VCCAUX is required.
When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to VCCAUX for a valid logic High.
When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
The input path from DONE pin input back to the Startup sequencer is not pipelined.
This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
Internally connects a pull-up resistor or between PROG_B pin and VCCAUX. An
external 4.7 kΩ pull-up resistor to VCCAUX is still recommended.
No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to
VCCAUX is required.
Internally connects a pull-up resistor between JTAG TCK pin and VCCAUX.
Internally connects a pull-down resistor between JTAG TCK pin and GND.
No internal pull-up resistor on JTAG TCK pin.
Internally connects a pull-up resistor between JTAG TDI pin and VCCAUX.
Internally connects a pull-down resistor between JTAG TDI pin and GND.
No internal pull-up resistor on JTAG TDI pin.
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Start-Up, page
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Description
91.
91.
Functional Description
93