XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 90

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Slave Serial Mode
In Slave Serial mode (M[2:0] = <1:1:1>), an external host
such as a microprocessor or microcontroller writes serial
configuration data into the FPGA, using the synchronous
serial interface shown in
data is presented on the FPGA’s DIN input pin with suffi-
cient setup time before each rising edge of the externally
generated CCLK clock input.
The intelligent host starts the configuration process by puls-
ing PROG_B and monitoring that the INIT_B pin goes High,
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
•
•
•
•
Configuration
Internal memory
Disk drive
Over network
Over RF link
Memory
Source
Download Host
Intelligent
R
Recommend
open-drain
PROG_B
•
•
•
Microcontroller
Processor
Tester
driver
READ/WRITE
DATA[7:0]
VCC
GND
PROG_B
SELECT
V
CLOCK
INIT_B
TMS
TDO
TCK
DONE
BUSY
TDI
JTAG
2.5V
Figure
60. The serial configuration
Figure 59: Daisy-Chaining using Slave Parallel Mode
Parallel
Slave
Mode
‘1’
‘1’
‘0’
‘0’
P
HSWAP
M2
M1
M0
D[7:0]
BUSY
CSI_B
RDWR_B
CCLK
TDI
TMS
TCK
PROG_B
Spartan-3E
VCCINT
+1.2V
FPGA
GND
VCCAUX
VCCO_0
VCCO_1
VCCO_2
www.xilinx.com
CSO_B
INIT_B
DONE
LDC0
LDC1
LDC2
HDC
TDO
VCCO_0
VCCO_1
+2.5V
V
V
indicating that the FPGA is ready to receive its first data.
The host then continues supplying data and clock signals
until either the DONE pin goes High, indicating a successful
configuration, or until the INIT_B pin goes Low, indicating a
configuration error. The configuration process requires
more clock cycles than indicated from the configuration file
size. Additional clocks are required during the FPGA’s
start-up sequence, especially if the FPGA is programmed to
wait for selected Digital Clock Managers (DCMs) to lock to
their respective clock inputs (see
+2.5V
Parallel
Slave
Mode
P
‘1’
‘1’
‘0’
‘0’
HSWAP
M2
M1
M0
D[7:0]
BUSY
CSI_B
RDWR_B
CCLK
TDI
PROG_B
TMS
TCK
Spartan-3E
VCCINT
FPGA
+1.2V
GND
VCCAUX
VCCO_0
VCCO_1
VCCO_2
Start-Up, page
CSO_B
INIT_B
DONE
Functional Description
LDC0
LDC1
LDC2
HDC
TDO
VCCO_0
VCCO_1
+2.5V
V
DS312-2_53_022305
91).
D[7:0]
CCLK
CSO_B
PROG_B
DONE
INIT_B
TMS
TCK
83