XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet - Page 129

• Manufacturer Part Number: XC3S100E-4TQG144I
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4TQG144I

• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 108
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pinout Descriptions
User I/Os by Bank
Table 8
tributed between the four I/O banks on the VQ100 package.
Table 8: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package
Footprint Migration Differences
The production XC3S100E and XC3S250E FPGAs have
identical footprints in the VQ100 package. Designs can
migrate between the XC3S100E and XC3S250E without
further consideration.
The pinout changed slightly between the XC3S100E engi-
neering samples and the production devices, as shown in
Table
M1 and M0 overlap with two global clock inputs feeding the
bottom-edge global buffers and DCMs. In the production
devices, the mode pins are swapped with parallel mode
data pins, D1 and D2. This way, these two mode pins do not
interfere with global clock inputs.
8
Top
Right
Bottom
Left
TOTAL
Package
Edge
9. In the engineering samples, the mode select pins
indicates how the 66 available user-I/O pins are dis-
I/O Bank
0
1
2
3
Maximum
I/O
15
15
19
17
66
I/O
16
5
6
0
5
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INPUT
0
0
0
1
1
Table 9: XC3S100E Pinout Changes between
Production Devices and Engineering Samples
All Possible I/O Pins by Type
VQ100 Pin
P40
P41
P42
P43
DUAL
18
21
1
0
2
Production
XC3S100E
D2/GCLK2
D1/GCLK3
Devices
M1
M0
Advance Product Specification
DS312-4 (v1.1) March 21, 2005
VREF
1
1
1
1
4
Engineering
XC3S100E
M1/GCLK2
M0/GCLK3
Samples
D2
D1
GCLK
24
8
8
0
8
R