CY7C66113-PVC Cypress Semiconductor Corp, CY7C66113-PVC Datasheet - Page 29

• Manufacturer Part Number: CY7C66113-PVC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113-PVC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1330

During a WDR, the Processor Status and Control Register is set to 01XX0001, which indicates a WDR (bit 6 set) has occurred
and no interrupts are pending (bit 7 clear). The WDR does not effect the state of the POR and the Bus Reset Interrupt bits.
16.0
Interrupts are generated by the GPIO/DAC pins, the internal timers, I
on various USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point
Interrupt Enable Register. Writing a ‘1’ to a bit position enables the interrupt associated with that bit position.
Global Interrupt Enable Register
Bit 0 : USB Bus RST Interrupt Enable
Bit 1 :128- s Interrupt Enable
Bit 2 : 1.024-ms Interrupt Enable
Bit 3 : USB Hub Interrupt Enable
Bit 4 : Reserved
Bit 5 : GPIO Interrupt Enable
Bit 6 : I
Bit 7 : Reserved.
USB Endpoint Interrupt Enable
Bit 0: EPA0 Interrupt Enable
Bit 1: EPA1 Interrupt Enable
Bit 2: EPA2 Interrupt Enable
Bit 3: EPB0 Interrupt Enable
Bit 4: EPB1 Interrupt Enable
Bit [7..5] : Reserved
Document #: 38-08024 Rev. *A
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
1= Enable Interrupt on a USB Bus Reset; 0 = Disable interrupt on a USB Bus Reset (refer to section 14.3).
1 = Enable Timer interrupt every 128 s; 0 = Disable Timer Interrupt for every 128 s.
1= Enable Timer interrupt every 1.024 ms ; 0 = Disable Timer Interrupt every 1.024 ms.
1 = Enable Interrupt on a Hub status change; 0 = Disable interrupt due to hub status change. (Refer to section 14.6.)
1 = Enable Interrupt on falling/rising edge on any GPIO; 0 = Disable Interrupt on falling/rising edge on any GPIO. (Refer to
subsections 14.7, 9.1, and 9.2.)
1= Enable Interrupt on I2C related activity; 0 = Disable I2C related activity interrupt. (Refer to section 14.8.)
1= Enable Interrupt on data activity through endpoint A0; 0= Disable Interrupt on data activity through endpoint A0.
1= Enable Interrupt on data activity through endpoint A1; 0= Disable Interrupt on data activity through endpoint A1.
1= Enable Interrupt on data activity through endpoint A2; 0= Disable Interrupt on data activity through endpoint A2.
1= Enable Interrupt on data activity through endpoint B0; 0= Disable Interrupt on data activity through endpoint B0.
1= Enable Interrupt on data activity through endpoint B1; 0= Disable Interrupt on data activity through endpoint B1.
2
C Interrupt Enable
Interrupts
7
Reserved
-
-
7
Reserved
-
-
R/W
6
I
Enable
0
6
Reserved
-
-
2
C Interrupt
Figure 16-2. USB Endpoint Interrupt Enable Register
Figure 16-1. Global Interrupt Enable Register
5
GPIO Interrupt
Enable
R/W
0
5
Reserved
-
-
4
Reserved
-
X
4
EPB1 Interrupt
Enable
R/W
0
2
C-compatible or HAPI operation, the internal USB hub, or
3
Interrupt
Enable
R/W
0
3
Enable
R/W
0
EPB0 Interrupt
USB Hub
2
1.024-ms
Interrupt
Enable
R/W
0
2
EPA2 Interrupt
Enable
R/W
0
1
Interrupt
Enable
R/W
0
1
EPA1 Interrupt
Enable
R/W
0
128- s
CY7C66013
CY7C66113
Page 29 of 58
ADDRESS 0X20
ADDRESS 0X21
0
USB Bus RST
Interrupt
Enable
R/W
0
0
EPA0 Interrupt
Enable
R/W
0