MPC8308CVMAFD Freescale Semiconductor, MPC8308CVMAFD Datasheet - Page 35

• Manufacturer Part Number: MPC8308CVMAFD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8308CVMAFD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 333 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Core Size: 32 Bit
• Cpu Speed: 333MHz
• Digital Ic Case Style: MAPBGA
• No. Of Pins: 473
• Operating Temperature Range: -40°C To +105°C
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.2.4.1
SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread
spectrum clock source.
10.3
Figure 26
The DC and AC specification of SerDes data lanes are defined in
Note that external AC coupling capacitor is required for the PCI Express serial transmission protocol with
the capacitor value defined in specification of PCI Express protocol section.
11 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus.
11.1
For more information, see
11.2
Table 33
Freescale Semiconductor
Symbol
t
t
REFCJ
REFPJ
t
REF
lists the PCI Express SerDes clock AC requirements.
SerDes Transmitter and Receiver Reference Circuits
DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
AC Requirements for PCI Express SerDes Clocks
shows the reference circuits for SerDes data lane’s transmitter and receiver.
REFCLK cycle time (for 125 MHz and 100 MHz)
REFCLK cycle-to-cycle jitter. Difference in the period
of any two adjacent REFCLK cycles.
Phase jitter. Deviation in edge location with respect to
mean edge location.
Spread Spectrum Clock
Transmitter
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
Figure 26. SerDes Transmitter and Receiver Reference Circuits
Table 33. SD_REF_CLK and SD_REF_CLK AC Requirements
Parameter Description
Section 10.2, “SerDes Reference Clocks.”
50 Ω
50 Ω
TX n
TX n
RX n
RX n
Min
–50
—
8
Section 11, “PCI Express.”
Typ
10
—
—
50 Ω
50 Ω
Receiver
Max
100
50
—
Units
ns
ps
ps
PCI Express
Notes
—
—
—
35