MPC8572ECVTAULD Freescale Semiconductor, MPC8572ECVTAULD Datasheet - Page 14

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MPC8572ECVTAULD

Manufacturer Part Number
MPC8572ECVTAULD
Description
MPU POWERQUICC III 1023-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8572ECVTAULD

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.333GHz
Voltage
1.1V
Mounting Type
Surface Mount
Package / Case
1023-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Part Number:
MPC8572ECVTAULD
Manufacturer:
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Quantity:
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Electrical Characteristics
2.1.3
Table 3
2.2
The MPC8572E requires its power rails to be applied in a specific sequence to ensure proper device
operation. These requirements are as follows for power up:
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before
the voltage rails on the current step reach 10% of theirs.
To guarantee MCKE low during power-on reset, the above sequencing for GV
concern about any of the DDR signals being in an indeterminate state during power-on reset, then the
sequencing for GV
14
Local bus interface utilities signals
DDR2 signal
DDR3 signal
eTSEC/10/100 signals
DUART, system control, JTAG
I2C
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at T
1. V
2. GV
XV
provides information on the characteristics of the output driver strengths.
DD
Power Sequencing
DD_SRDS2
DD
Output Driver Characteristics
, AV
From a system standpoint, if any of the I/O power supplies ramp prior to the
VDD core supply, the I/Os associated with that I/O supply may drive a logic
one or zero during power-on reset, and extra current may be drawn by the
device.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
DD
DD
_n, BV
Driver Type
is not required.
DD
, LV
DD
Table 3. Output Drive Capability
, OV
DD
, SV
NOTE
DD_SRDS1
36 (half strength mode)
40 (half strength mode)
Output Impedance
Programmable
45(default)
45(default)
125
150
(Ω)
25
35
18
20
45
45
and SV
DD_SRDS2
j
= 105°C and at GV
L/TV
BV
BV
BV
BV
BV
GV
GV
OV
OV
, TV
DD
DD
Voltage
Supply
DD
DD
DD
DD
DD
DD
DD
DD
DD
is required. If there is no
= 2.5/3.3 V
DD
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 1.8 V
= 3.3 V
= 3.3 V
= 1.8 V
= 1.5 V
Freescale Semiconductor
, XV
DD
DD_SRDS1
(min).
Notes
1
2
2
and

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