MPC8572ECVTAULD Freescale Semiconductor, MPC8572ECVTAULD Datasheet - Page 74

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MPC8572ECVTAULD

Manufacturer Part Number
MPC8572ECVTAULD
Description
MPU POWERQUICC III 1023-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8572ECVTAULD

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.333GHz
Voltage
1.1V
Mounting Type
Surface Mount
Package / Case
1023-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Part Number:
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High-Speed Serial Interfaces (HSSI)
15.2.2
The DC level requirement for the MPC8572E SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
74
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to
The input amplitude requirement
— This requirement is described in detail in the following sections.
Differential Mode
— The input amplitude of the differential clock must be between 400mV and 1600mV differential
Differential Mode and Single-ended Mode description below for further detailed requirements.
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), because the
input is AC-coupled on-chip.
(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source from 0 mA to 16 mA (0-0.8 V), such that
each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
must be AC-coupled off-chip.
peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire
DC Level Requirement for SerDes Reference Clocks
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Figure 44. Receiver of SerDes Reference Clocks
SD n _REF_CLK
SD n _REF_CLK
50 Ω
50 Ω
Input
Amp
Freescale Semiconductor

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