MPC8572ECVTAULD Freescale Semiconductor, MPC8572ECVTAULD Datasheet - Page 56

• Manufacturer Part Number: MPC8572ECVTAULD
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572ECVTAULD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller (eLBC)
Table 51
56
At recommended operating conditions with BV
At recommended operating conditions with BV
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and
LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
6. t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
8. Guaranteed by design.
Local bus cycle time
Local bus duty cycle
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
LALE output negation to high impedance for LAD/LDP
(LATCH hold time)
Table 50. Local Bus General Timing Parameters (BV
(reference)(state)
t
reference (K) goes high (H), in this case for clock one(1). Also, t
t
for PLL bypass mode to 0.4 × BV
delivered through the component pin is less than or equal to the leakage current specification.
is programmed with the LBCR[AHD] parameter.
complementary signals at BV
LBIXKH1
LBK
LBOTOT
describes the general timing parameters of the local bus interface at BV
clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
Table 51. Local Bus General Timing Parameters (BV
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
for inputs and t
Parameter
Parameter
DD
(First two letters of functional block)(reference)(state)(signal)(state)
DD
DD
/2.
DD
DD
of 2.5 V ± 5% (continued)
of 1.8 V ± 5%
/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock
of the signal in question for 2.5-V signaling levels.
Symbol
t
t
t
t
t
t
t
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
LBKHOX2
LBKHOZ1
LBKHOZ2
Symbol
t
t
LBKH/
LBKSKEW
t
t
t
t
t
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBOTOT
DD
t
LBK
1
LBKHOX
t
LBK
= 2.5 V DC)—PLL Enabled (continued)
1
DD
Min
0.8
0.8
—
—
—
—
—
(First two letters of functional block)(signal)(state)
symbolizes local bus timing (LB) for the
= 1.8 V DC)—PLL Enabled
6.67
Min
2.4
1.9
1.1
1.1
1.2
43
—
Max
2.5
2.4
2.4
2.6
2.6
—
—
for outputs. For example,
Max
150
12
57
—
—
—
—
—
DD
Freescale Semiconductor
= 1.8 V DC
Unit
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ps
ns
ns
ns
ns
ns
%
LBK
Notes
Notes
LBOTOT
7, 8
3, 4
3, 4
3, 4
3, 4
clock
—
3
3
3
3
3
5
5
2
6