MPC8572ECVTAULD Freescale Semiconductor, MPC8572ECVTAULD Datasheet - Page 30

• Manufacturer Part Number: MPC8572ECVTAULD
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572ECVTAULD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.2
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this
section.
8.2.1
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI
specifications, because they have similar performance and are described in a source-synchronous fashion
like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back on
the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended
that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-
synchronous timing reference. Typically, the clock edge that launched the data can be used, because the
clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is a
relationship between the maximum FIFO speed and the platform (CCB) frequency. For more information
see
Table 25
30
At recommended operating conditions with LV
TX_CLK, GTX_CLK clock period
TX_CLK, GTX_CLK duty cycle
TX_CLK, GTX_CLK peak-to-peak jitter
1
2
3
Input high current
(V
Input low current
(V
Note:
LV
TV
Note that the symbol V
Section 4.5, “Platform to eTSEC FIFO Restrictions.”
IN
IN
DD
= LV
= GND)
DD
Table 24. MII, GMII, RMII, RGMII, TBI, RTBI, and FIFO DC Electrical Characteristics (continued)
supports eTSECs 1 and 2.
supports eTSECs 3 and 4 or FEC.
and
DD
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
, V
FIFO AC Specifications
Table 26
IN
Parameters
= TV
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter/Condition
DD
)
IN
summarize the FIFO AC specifications.
, in this case, represents the LV
Table 25. FIFO Mode Transmit AC Timing Specification
1
DD
/TV
DD
Symbol
of 2.5V ± 5%
I
I
IH
IL
IN
and TV
t
Symbol
FITH
Min
–15
t
—
t
FITJ
FIT
/t
FIT
IN
symbols referenced in
Min
5.3
45
—
Max
10
—
Typ
8.0
50
—
Table
Freescale Semiconductor
1.
Unit
μA
μA
Max
100
250
55
Notes
1, 2,3
3
Unit
ns
ps
%