MPC8572ECVTAULD Freescale Semiconductor, MPC8572ECVTAULD Datasheet - Page 21

• Manufacturer Part Number: MPC8572ECVTAULD
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572ECVTAULD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

this section for DDR3 is applicable for data rate between 606 MHz and 800 MHz, as long as the DC and
AC specifications of the DDR3 memory to be used are compliant to both JEDEC specifications as well as
the specifications and requirements described in this MPC8572E hardware specifications document.
6.2.1
Table
interfacing to DDR2 and DDR3 SDRAM.
Freescale Semiconductor
At recommended operating conditions with GV
At recommended operating conditions with GV
At recommended operating conditions with GV
AC input low voltage
AC input high voltage
Controller Skew for MDQS—MDQ/MECC
800 MHz
667 MHz
533 MHz
400 MHz
Note:
1. t
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
AC input low voltage
AC input high voltage
bit that is captured with MDQS[n]. This should be subtracted from the total timing budget.
determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and
abs(tCISKEW) is the absolute value of tCISKEW.
15,
CISKEW
Table
—
Table 15. DDR2 SDRAM Interface Input AC Timing Specifications for 1.8-V Interface
Table 16. DDR3 SDRAM Interface Input AC Timing Specifications for 1.5-V Interface
DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding
Parameter
Parameter
Table 17. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
16, and
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter
>=667 MHz
<= 533 MHz
>=667 MHz
<= 533 MHz
Table 17
provide the input AC timing specifications for the DDR controller when
DD
DD
DD
of 1.8 V ± 5%
of 1.5 V ± 5%. DDR3 data rate is between 606 MHz and 800 MHz.
of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
Symbol
V
V
Symbol
IHAC
ILAC
V
V
IHAC
ILAC
Symbol
t
CISKEW
—
—
—
—
MV
MV
MV
REF
Min
REF
REF
—
n + 0.175
Min
—
—
n + 0.20
n + 0.25
–200
–240
–300
–365
Min
—
MV
MV
MV
REF
Max
REF
REF
n – 0.175
—
Max
Max
—
—
200
240
300
365
n – 0.20
n – 0.25
—
DDR2 and DDR3 SDRAM Controller
Unit
Unit
V
V
ps
—
—
—
—
Unit
V
V
Notes
Notes
—
—
1, 2
Notes
—
—
—
—
—
—
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