DP83907VF National Semiconductor, DP83907VF Datasheet

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... DP83907’s ENDEC module and the twisted pair medium 1 0 System Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation AT LANTIC trademark of National Semiconductor Corporation Ethernet is a registered trademark of Xerox Corporation ...

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General Description (Continued) The integrated ENDEC module allows Manchester encod- ing and decoding via a differential transceiver and phase lock loop decoder at 10 Mbit sec Also included are a colli- sion detect translator and diagnostic loopback capability The ENDEC ...

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... Connection Diagram Order Number DP83907VF See NS Package Number VF132A 12082– 2 ...

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Pin Description Pin No Pin Name Type ISA BUS INTERFACE PINS 119–127 SA0–SA9 I 132 TTL 1 –7 SA13–SA19 I TTL 10 11 SMRD I SMWR TTL SD0–SD7 SD8–SD15 3ST ...

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Pin Description (Continued) Pin No Pin Name Type NETWORK INTERFACE PINS 44 –47 TxOd TXO O TWISTED PAIR TRANSMIT OUTPUTS These high drive CMOS level outputs are a b resistively combined external to the chip to produce a ...

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Pin Description (Continued) Pin No Pin Name Type EXTERNAL MEMORY SUPPORT 87 –94 MSD0 – O– I–O MEMORY SUPPORT DATA BUS CONFIGURATION REGISTER A INPUT EEPROM SIGNALS CA0 –7 or MOS MSD0–7 When RESET is inactive ...

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Pin Description (Continued) Pin No Pin Name Type EXTERNAL MEMORY SUPPORT (Continued) 95 RCS O MOS 97 BPCS O MOS 96 EECS O MOS POWER SUPPLY PINS AGND TPV CC CC ...

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Simplified Application Diagram 12082 – 3 ...

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Simplified Application Diagram 4 0 Functional Description The DP83907 is a highly integrated and configurable Ether- net controller making it suitable for most Ethernet applica- tions The DP83907 integrates the functions of the following blocks 1 ISA Bus ...

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Functional Description FIGURE Port The DP83907’s internal memory map is accessed one byte or word at a time via a port within the systems I O space DP83907 is programmed by the user to control ...

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Functional Description On a remote read the DP83907 moves data from its internal memory map to the I O port and the host system reads it by using an ‘‘INW’’ or ‘‘INSW’’ instruction from the I O address ...

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Functional Description The ISA standard determines that within 500 ns of RESET going active all devices should enter the appropriate reset condition The DP83907 will generate the internal signal IOinactive after RESET has been active for 400 ns ...

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Functional Description dure should be followed exactly and interrupts should be disabled until it has completed to prevent any accidental accesses to the DP83907 EEPROM LOAD() DISABLE INTERRUPTS() value READ(CONFIG B) value value AND GDLINK value value OR ...

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Functional Description FIGURE 12 DP8390 Core Simplified Block Diagram ing the last transmit byte During reception the CRC logic generates a CRC field from the incoming packet This local CRC is serially compared to the incoming CRC appended ...

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Functional Description FIFO underruns or overruns are caused when a local DMA request is issued while an ISA bus access is current and the ISA cycle takes longer to complete than the local DMA’s tolerable latency This tolerable ...

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Functional Description FIGURE 13 Twisted Pair Interface Module Block Diagram A second DMA channel (Remote DMA) is used as a slave DMA to transfer data between the local buffer memory and the host system The Local DMA and ...

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Functional Description Receiver and Smart Squelch The DP83907 implements an intelligent receive squelch on the RXI differential inputs to ensure that impulse noise on g the receive inputs will not be mistaken for a valid signal The squelch ...

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Functional Description Transmitter The transmitter consists of four signals the true and compli- ment Manchester encoded data (TXO ) and these signals g delayed (TXOd ) g These four signals are resistively combined TXO TXOd ...

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Functional Description FIGURE 16b Circuitry to Connect DP83907 to Twisted Pair Cable with Internal Filter On-Chip Filters The on-chip filters are enabled via an external pull-up resis- tors on MSD 12 at configuration Only an isolation trans- k ...

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Functional Description FIGURE 18 Encoder Decode Block Diagram 4 10 ENCODER DECODER (ENDEC) MODULE The ENDEC consists of four main logical blocks a) The oscillator generates the 10 MHz transmit clock sig- nal for system timing b) The ...

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Functional Description If a crystal is connected to the DP83907 it is recommended that the circuit shown in Figure 19 be used and that the components used meet the following Crystal XT1 AT cut parallel resonant crystal Series ...

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Functional Description Manchester Decoder The decoder consists of a differential receiver and a PLL to separate a Manchester encoded data stream into internal clock signals and data The differential input must be exter- nally terminated with two 39 ...

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Register Descriptions 5 1 CONFIGURATION REGISTERS These registers are used to configure the operation of the DP83907 typically after power up These registers control the configuration of bus interface setting options like interrupt selection I O base address ...

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Register Descriptions MODE CONFIGURATION REGISTER B To prevent any accidental writes of this register it is ‘‘hidden’’ behind a previously unused register Register 0BH in the DP83907’s Page 0 of registers was previously reserved on a read Now ...

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Register Descriptions HARDWARE CONFIGURATION REGISTER C This register is configured during a RESET and can be accessed by 3rd consecutive read config register SOFEN RES Bit Symbol 0–3 BPS0–3 BOOT PROM SELECT Selects address at ...

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Register Descriptions SIGNATURE REGISTER This register is intended to allow the software programmer to determine which of the DP83907 family of devices and what board configuration is being used This register is ‘‘hidden’’ behind a used register Register ...

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Register Descriptions (Continued NIC CORE REGISTERS All registers are 8-bit wide and mapped into two pages which are selected in the Command Register (PS0 PS1) Pins RA0– RA3 are used to address registers within each page ...

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Register Descriptions (Continued) Page 1 Address Assignments (PS1 RA0–RA3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 0 PS0 Command (CR) Command (CR) Physical Address ...

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Register Descriptions (Continued) Page 2 Address Assignments (PS1 RA0–RA3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Note Page 2 registers should only be accessed for diagnostic purposes They should ...

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Register Descriptions COMMAND REGISTER (CR) 00H (READ WRITE) The Command Register is used to initiate transmissions enable or disable Remote DMA operations and to select register pages To issue a command the microprocessor sets the corresponding bit(s) (RD2 ...

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Register Descriptions INTERRUPT STATUS REGISTER (ISR) This register is accessed by the host processor to determine the cause of an interrupt Any interrupt can be masked in the Interrupt Mask Register (IMR) Individual interrupt bits are cleared by ...

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Register Descriptions INTERRUPT MASK REGISTER (IMR) The Interrupt Mask Register is used to mask interrupts Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR interrupt mask bit is set an interrupt ...

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Register Descriptions DATA CONFIGURATION REGISTER (DCR) This Register is used to program the DP83907 for 8- or 16-bit memory interface select byte ordering in 16-bit applications and establish FIFO thresholds The DCR must be initialized prior to loading ...

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Register Descriptions TRANSMIT CONFIGURATION REGISTER (TCR) The transmit configuration establishes the actions of the transmitter section of the DP83907 during transmission of a packet on the network LB1 and LB0 which select loopback mode power ...

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Register Descriptions TRANSMIT STATUS REGISTER (TSR) This register records events that occur on the media during transmission of a packet It is cleared when the next transmission is initiated by the host All bits remain low unless the ...

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Register Descriptions RECEIVE CONFIGURATION REGISTER (RCR) This register determines operation of the DP83907 during reception of a packet and is used to program what types of packets to accept 7 6 Bits Symbols D0 SEP SAVE ERRORED PACKETS ...

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Register Descriptions RECEIVE STATUS REGISTER (RSR) This register records status of the received packet including information on errors and the type of address match either physical or multicast The contents of this register are written to buffer memory ...

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Register Descriptions (Continued DP8390 CORE DMA REGISTERS The DMA Registers are partitioned into groups Transmit Receive and Remote DMA Registers The Transmit regis- ters are used to initialize the Local DMA Channel for trans- mission of ...

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Register Descriptions (Continued) Local DMA Receive Registers PAGE START STOP REGISTERS (PSTART PSTOP) The Page Start and Page Stop Registers program the start- ing and stopping address of the Receive Buffer Ring Since the DP83907 uses fixed 256-byte ...

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Register Descriptions (Continued) tem designer would use a program to determine which filter bits to set in the multicast registers All multicast filter bits that correspond to multicast address accepted by the node are then set to one ...

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Operation of DP83907 (Continued) FIGURE 27 DP83907 Bus Architecture 6 2 BUFFER MEMORY ACCESS CONTROL (DMA) The buffer memory control capabilities of the DP83907 greatly simplify the use of the DP83907 in typical configura- tions The local DMA ...

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Operation of DP83907 (Continued PACKET RECEPTION The Local DMA receive channel uses a Buffer Ring Struc- ture comprised of a series of contiguous fixed length 256 byte (128 word) buffers for storage of received packets The ...

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Operation of DP83907 (Continued) Linking Receive Buffer Pages If the length of the packet exhausts the first 256 byte buffer the DMA performs a forward link to the next buffer to store the remainder of the packet For ...

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Operation of DP83907 (Continued) 4) Clear the DP83907’s Remote Byte Count registers (RBCR0 and RBCR1) 5) Read the stored value of the TXP bit from step 1 above If this value set the ‘‘Resend’’ variable ...

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Operation of DP83907 (Continued) FIGURE 33 Received Packet Aborted if it Hits Boundary Enabling the DP83907 on an Active Network After the DP83907 has been initialized the procedure for disabling and then re-enabling the DP83907 on the network ...

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Operation of DP83907 (Continued) Error Recovery If the packet is rejected as shown the DMA is restored by the DP83907 by reprogramming the DMA starting address pointed to by the Current Page Register Storage Format for Received Packets ...

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Operation of DP83907 (Continued) Conditions Required to Begin Transmission In order to transmit a packet the following three conditions must be met 1 The Interframe Gap Timer has timed out the first the Interframe ...

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Operation of DP83907 (Continued LOOPBACK DIAGNOSTICS Three forms of local Ioopback are provided on the DP83907 The user has the ability to loopback through the deserializer on the controller through the ENDEC module or transceiver Because ...

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Operation of DP83907 (Continued) For the following alignment in the FIFO the packet length should Bytes Note that if the CRC bit in the a TCR is set CRC will not be appended ...

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Operation of DP83907 (Continued) CRC and Address Recognition The next three tests exercise the address recognition logic and CRC These tests should be performed using internal Ioopback only so that the DP83907 is isolated from interfer- ence from ...

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Operation of DP83907 (Continued) The idle state is exited and the DP83907 will drive the local memory bus when a request from the FIFO in the DP8390 (NIC) core causes the memory bus interface logic to issue a ...

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Operation of DP83907 (Continued) FIGURE 40 Remote DMA Auto Initialization from Buffer Ring next pkt Next Page Pointer e BNDRY Next Page Pointer BNDRY PSTART then BNDRY PSTOP k e Note the size of ...

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Operation of DP83907 (Continued) The DMA Address will be incremented and the Byte Coun- ter will be decremented after each transjer The DMA is terminated when the Remote Byte Count Register reaches zero Send Packet Command The Remote ...

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Operation of DP83907 (Continued) This is the type of cycle used to read from a register or in 8-bit mode from a data transfer port These accesses are entirely asynchronous with the DP83907 responding when it decodes the ...

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Operation of DP83907 (Continued) This is the type of cycle used to read from a data transfer port in 16-bit mode These accesses are entirely asynchronous with the DP83907 responding when it decodes the correct address on SA0– ...

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Operation of DP83907 (Continued) 16-Bit I O Cycle with IO16 Fix Some Chips Technologies and VLSI Technologies PC-AT chip sets have timing requirements in 16-bit I O cycles that cannot be achieved by the default DP83907 cycle described ...

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Operation of DP83907 (Continued) This is the type of cycle used to write to the boot PROM These accesses are entirely asynchronous with the DP83907 responding when it decodes the correct address on SA0-19 and a SMWR If ...

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Operation of DP83907 (Continued) RAM ACCESS TIMING This is a memory read cycle executed by the DP83907’s internal DMA This is used to either load the data transfer port during a Remote Read mode or ...

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In-Circuit Test (ICT) Description The test register is made available only when the test bit (D7 of cnfg A) is set at the following I O address The test register contains the following bits Note that when the ...

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... DP83907 Preliminary Specification Design Guide This document provides information on National Semiconductor’s DP83907 target design parametric specifications These specifications are provided as design targets for the DP83907 These parameters should be used to undergo systems design activities and are not provided as guaranteed parametric specifications At this time these specifications are not tested and are subject to change based upon National’ ...

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Preliminary DC Specifications Symbol Description OSCILLATOR PINS (X1 AND X2 Input High Voltage Input Low Voltage Input Current OSC TPI R TXOd TXO Low Level Output Resistance TOL TXOd ...

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Preliminary Switching Design Guidelines Memory Support Bus Accesses (for I O port or FIFO transfers) MEMORY SUPPORY BUS ACCESSES (for I O Port or FIFO Transfers) Symbol Description T1 MSA1–13 Valid before RCS Asserted T2 MSA1–13 Valid before MSRD–WR Asserted ...

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Preliminary Switching Design Guidelines ISA SLAVE ACCESSES (Continued 12082 – 45 ...

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Preliminary Switching Design Guidelines ISA SLAVE ACCESSES (Continued) Symbol Description T2 AEN Valid before Command Strobe Active T3a SA0–9 Valid before IORD IOWR Asserted T3b SA0–19 Valid before SMRD SMWR Asserted T4 SMRD IORD Asserted to SD0–15 Driven (Notes 3 ...

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Preliminary Switching Design Guidelines ISA SLAVE ACCESSES (Continued) Symbol Description T27 SA0–19 Valid to BPCS Asserted (Note 11) T28a MRD Asserted to MSRD Asserted T28b MWR Asserted to MSWR Asserted T30 SA0–19 Invalid to BPCS Negated (Note 11) T31 SMRD ...

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Preliminary Switching Design Guidelines TPI RECEIVE TIMING (End of Packet) Symbol t Receive End of Packet Hold Time after Logic ‘‘1‘‘ (Note 1) eop1 t Receive End of Packet Hold Time after Logic ‘‘0‘‘ (Note 1) eop0 Note 1 This ...

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Preliminary Switching Design Guidelines TPI TRANSMIT TIMING (End of Packet) Symbol Description t Pre-Emphasis Output Delay (TXO del t Transmit Hold Time at End of Packet (TXO Off t Transmit Hold Time at End of Packet (TXOd Offd Note 1 ...

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Preliminary Switching Design Guidelines AUI TRANSMIT TIMING (End of Packet) Symbol Description t Transmit Output High before Idle (Note 1) TOh t Transmit Output Idle Time (Note 1) TOI AUI RECEIVE TIMING (End of Packet) Symbol t Receive End of ...

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... Italiano National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Order Number DP83907VF NS Package Number VF132A 2 A critical component is any component of a life ...