DP83907VF National Semiconductor, DP83907VF Datasheet - Page 39

• Manufacturer Part Number: DP83907VF
• Description: IC CONTROLLR AT/LANII TP 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83907VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83907VF

5 0 Register Descriptions
Local DMA Receive Registers
PAGE START STOP REGISTERS (PSTART PSTOP)
The Page Start and Page Stop Registers program the start-
ing and stopping address of the Receive Buffer Ring Since
the DP83907 uses fixed 256-byte buffers aligned on page
boundaries only the upper eight bits of the start and stop
address are specified
PSTART PSTOP bit assignment
BOUNDARY (BNRY) REGISTER
This register is used to prevent overflow of the Receive
Buffer Ring Buffer management compares the contents of
this register to the next buffer address when linking buffers
together If the contents of this register match the next buff-
er address the Local DMA operation is aborted
CURRENT PAGE REGISTER (CURR)
This register is used internally by the Buffer Management
Logic as a backup register for reception CURR contains the
address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive
errors This register is initialized to the same value as
PSTART and should not be written to again unless the con-
troller is Reset
CURRENT LOCAL DMA REGISTER 0 1 (CLDA0 1)
These two registers can be accessed to determine the cur-
rent Local DMA Address
Remote DMA Registers
REMOTE START ADDRESS REGISTERS (RSAR0 1)
Remote DMA operations are programmed via the Remote
Start Address (RSAR0 1) and Remote Byte Count
(RBCR0 1) registers The Remote Start Address is used to
point to the start of the block of data to be transferred and
the Remote Byte Count is used to indicate the length of the
block (in bytes)
PSTART
BNRY
CURR
CLDA1
CLDA0
RSAR1
RSAR0
PSTOP
A15
A15
A15
A15
7
7
A7
A7
A15
7
7
7
7
7
A14
A14
A14
A14
6
A6
6
A6
A14
6
6
6
6
6
A13
A13
A13
A13
A5
A5
A13
5
5
5
5
5
5
5
A12
A12
A12
A12
A12
A4
A4
4
4
4
4
4
4
4
A11
A11
A11
A11
A11
A3
A3
3
3
3
3
3
3
3
(Continued)
A10
A10
A10
A10
A10
A2
A2
2
2
2
2
2
2
2
A9
A9
A9
A1
A9
A1
A9
1
1
1
1
1
1
1
A8
A8
A8
A8
A0
A8
A0
0
0
0
0
0
0
0
39
REMOTE BYTE COUNT REGISTERS (RCB0 1)
Note
RSAR0 programs the start address bits A0–A7
RSAR1 programs the start address bits A8–A15
Address incremented by two for word transfers and by one for byte trans-
fers Byte count decremented by two for word transfers and by one for byte
transfers
RBCR0 programs LSB byte count
RBCR1 programs MSB byte count
CURRENT REMOTE DMA ADDRESS (CRDA0 CRDA1)
The Current Remote DMA Registers contain the current ad-
dress of the Remote DMA The bit assignment is shown
below
Physical Address Registers (PAR0– PAR5)
The physical address registers are used to compare the
destination address of incoming packets for rejecting or ac-
cepting packets Comparisons are performed on a byte-
wide basis The bit assignment shown below relates the se-
quence in PAR0– PAR5 to the bit sequence of the received
packet
Note
P S
DA0
Multicast Address Registers (MAR0– MAR7)
The multicast address registers provide filtering of multicast
addresses hashed by the CRC logic All destination ad-
dresses are fed through the CRC logic and as the last bit of
the destination address enters the CRC the 6 most signifi-
cant bits of the CRC generator are latched These 6 bits are
then decoded by a 1 of 64 decode to index a unique filter bit
(FB0– 63) in the multicast address registers If the filter bit
selected is set the multicast packet is accepted The sys-
PAR0
PAR1
PAR2
PAR3
PAR4
PAR5
P S
RBCR1
RBCR0
CRDA1
CRDA0
e
e
Preamble Synch
Physical Muftcast Bit
DA0
DA15
DA23
DA31
DA39
DA47
DA7
D7
Destination Address
A15
A15
A7
A7
7
7
7
7
DA1
DA14
DA22
DA30
DA38
DA46
DA6
D6
A14
A14
A6
A6
6
6
6
6
DA2
DA13
DA21
DA29
DA37
DA45
DA5
D5
A13
A13
A5
A5
DA3
5
5
5
5
DA12
DA20
DA28
DA36
DA44
DA4
D4
A12
A12
A4
A4
4
4
4
4
DA11
DA19
DA27
DA35
DA43
DA3
D3
DA46
A11
A11
A3
A3
3
3
3
3
DA10
DA18
DA26
DA34
DA42
DA2
D2
DA47
A10
A10
A2
A2
2
2
2
2
DA17
DA25
DA33
DA41
Source
DA1
DA9
D1
A9
A1
A9
A1
SA0
1
1
1
1
DA16
DA24
DA32
DA40
DA0
DA8
D0
A8
A0
A8
A0
0
0
0
0