AD9959BCPZ Analog Devices Inc, AD9959BCPZ Datasheet - Page 18

• Manufacturer Part Number: AD9959BCPZ
• Description: IC DDS QUAD 10BIT DAC 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9959BCPZ

• Resolution (bits): 10 b
• Design Resources: Phase Coherent FSK Modulator (CN0186)
• Master Fclk: 500MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Sampling Rate: 500MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 1.71V To 1.89V
• Supply Current: 160mA
• Digital Ic Case Style: CSP
• Data Interface: Serial, SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9959
THEORY OF OPERATION
DDS CORE
The AD9959 has four DDS cores, each consisting of a 32-bit
phase accumulator and phase-to-amplitude converter. Together,
these digital blocks generate a digital sine wave when the phase
accumulator is clocked and the phase increment value (frequency
tuning word) is greater than 0. The phase-to-amplitude converter
simultaneously translates phase information to amplitude
information by a cos(θ) operation.
The output frequency (f
of the rollover rate of each phase accumulator. The exact
relationship is given in the following equation:
where:
f
FTW is the frequency tuning word and is 0 ≤ FTW ≤ 2
2
Because all four channels share a common system clock, they
are inherently synchronized.
The DDS core architecture also supports the capability to phase
offset the output signal, which is performed by the channel
phase offset word (CPOW). The CPOW is a 14-bit register that
stores a phase offset value. This value is added to the output of
the phase accumulator to offset the current phase of the output
signal. Each channel has its own phase offset word register. This
feature can be used for placing all channels in a known phase
relationship relative to one another. The exact value of phase
offset is given by the following equation:
S
32
is the system clock rate.
represents the phase accumulator capacity.
Φ
f
OUT
=
⎛
⎜
⎝
=
POW
2
(
14
FTW
2
⎞
⎟
⎠
32
×
)(
360
f
S
)
OUT
°
) of each DDS channel is a function
31
.
Rev. B | Page 18 of 44
DIGITAL-TO-ANALOG CONVERTER
The AD9959 incorporates four 10-bit current output DACs.
The DAC converts a digital code (amplitude) into a discrete
analog quantity. The DAC current outputs can be modeled as a
current source with high output impedance (typically 100 kΩ).
Unlike many DACs, these current outputs require termination
into AVDD via a resistor or a center-tapped transformer for
expected current flow.
Each DAC has complementary outputs that provide a combined
full-scale output current (I
current, and their sum equals the full-scale current at any point
in time. The full-scale current is controlled by means of an
external resistor (R
bits discussed in the Modes of Operation section. The resistor,
R
ground (AGND). The full-scale current is inversely proportional
to the resistor value as follows:
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides
optimal spurious-free dynamic range (SFDR) performance.
The DAC output voltage compliance range is AVDD + 0.5 V to
AVDD − 0.5 V. Voltages developed beyond this range may cause
excessive harmonic distortion. Proper attention should be paid
to the load termination to keep the output voltage within its
compliance range. Exceeding this range could potentially dam-
age the DAC output circuitry.
SET
, is connected between the DAC_RSET pin and analog
R
SET
Figure 32. Typical DAC Output Termination Configuration
=
I
OUT
DAC
18
.
(max)
91
SET
) and the scalable DAC current control
CHx_IOUT
CHx_IOUT
AVDD
OUT
+ I
OUT
1:1
). The outputs always sink
LPF
50Ω