AD9959BCPZ Analog Devices Inc, AD9959BCPZ Datasheet - Page 2

• Manufacturer Part Number: AD9959BCPZ
• Description: IC DDS QUAD 10BIT DAC 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9959BCPZ

• Resolution (bits): 10 b
• Design Resources: Phase Coherent FSK Modulator (CN0186)
• Master Fclk: 500MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Sampling Rate: 500MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 1.71V To 1.89V
• Supply Current: 160mA
• Digital Ic Case Style: CSP
• Data Interface: Serial, SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9959
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings ............................................................ 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Application Circuits ....................................................................... 14
Equivalent Input and Output Circuits ......................................... 17
Theory of Operation ...................................................................... 18
Modes of Operation ....................................................................... 19
REVISION HISTORY
7/08—Rev. A to Rev. B
Added Pin Profile Toggle Rate Parameter in Table 1 ................... 6
Changes to Figure 24 ...................................................................... 14
Changes to Figure 31 ...................................................................... 17
Changes to Reference Clock Input Circuitry Section ................ 20
Changes to Operation Section ...................................................... 29
Changes to Figure 40 ...................................................................... 30
Changes to Serial Data I/O (SDIO_0, SDIO_1, SDIO_3)
Section .............................................................................................. 32
Changes to Table 38 ........................................................................ 43
Added Exposed Pad Notation to Outline Dimensions ............. 44
3/08—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Inserted Figure 1 ............................................................................... 1
Changes to Input Level Specification ............................................. 4
Changes to Layout ............................................................................ 8
Changes to Table 3 ............................................................................ 9
ESD Caution .................................................................................. 8
DDS Core ..................................................................................... 18
Digital-to-Analog Converter .................................................... 18
Channel Constraint Guidelines ................................................ 19
Power Supplies ............................................................................ 19
Single-Tone Mode ...................................................................... 19
Reference Clock Modes ............................................................. 20
Scalable DAC Reference Current Control Mode ................... 21
Power-Down Functions ............................................................. 21
Modulation Mode ....................................................................... 21
Modulation Using SDIO_x Pins for RU/RD........................... 24
Rev. B | Page 2 of 44
Synchronizing Multiple AD9959 Devices ................................... 29
Serial I/O Port ................................................................................. 31
Register Maps and Bit Descriptions ............................................. 36
Outline Dimensions ....................................................................... 44
Added Equivalent Input and Output Circuits Section .............. 17
Changes to Figure 35 ...................................................................... 21
Changes to Setting the Slope of the Linear Sweep Section ....... 25
Changes to Frequency Linear Sweep Example: AFP Bits = 10
Section .............................................................................................. 26
Changes to Figure 37 ...................................................................... 26
Changes to Figure 38 and Figure 39............................................. 27
Added Table 25 ............................................................................... 31
Changes to Figure 41 ...................................................................... 31
Changes to Figure 42 ...................................................................... 32
Added Example Instruction Byte Section ................................... 32
Added Table 27 ............................................................................... 33
Changes to Figure 46, Figure 47, Figure 48, and Figure 49....... 35
Changes to Register Maps and Bit Descriptions Section .......... 36
Added Endnote 1 to Table 30 ........................................................ 38
Changes to Ordering Guide .......................................................... 44
7/05—Revision 0: Initial Version
Linear Sweep Mode .................................................................... 25
Linear Sweep No-Dwell Mode ................................................. 26
Sweep and Phase Accumulator Clearing Functions .............. 27
Output Amplitude Control Mode ............................................ 28
Automatic Mode Synchronization ........................................... 29
Manual Software Mode Synchronization ................................ 29
Manual Hardware Mode Synchronization .............................. 29
I/O_UPDATE, SYNC_CLK, and System Clock
Relationships ............................................................................... 30
Overview ..................................................................................... 31
Instruction Byte Description .................................................... 32
Serial I/O Port Pin Description ................................................ 32
Serial I/O Port Function Description ...................................... 32
MSB/LSB Transfer Description ................................................ 32
Serial I/O Modes of Operation ................................................. 33
Register Maps .............................................................................. 36
Descriptions for Control Registers .......................................... 39
Descriptions for Channel Registers ......................................... 41
Ordering Guide .......................................................................... 44