AD9959BCPZ Analog Devices Inc, AD9959BCPZ Datasheet - Page 40

• Manufacturer Part Number: AD9959BCPZ
• Description: IC DDS QUAD 10BIT DAC 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9959BCPZ

• Resolution (bits): 10 b
• Design Resources: Phase Coherent FSK Modulator (CN0186)
• Master Fclk: 500MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Sampling Rate: 500MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 1.71V To 1.89V
• Supply Current: 160mA
• Digital Ic Case Style: CSP
• Data Interface: Serial, SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9959
Bit
5
4
3:2
1
0
Function Register 2 (FR2)—Address 0x02
Two bytes are assigned to this register. The FR2 is used to control the various functions, features, and modes of the AD9959.
Table 33. Bit Descriptions for FR2
Bit
15
14
13
12
11:8
7
6
5
4
3: 2
1:0
Mnemonic
SYNC_CLK disable
DAC reference power-down
Open
Manual hardware sync
Manual software sync
Mnemonic
All channels autoclear sweep
accumulator
All channels clear
sweep accumulator
All channels autoclear phase
accumulator
All channels clear phase
accumulator
Open
Auto sync enable
Multidevice sync master enable
Multidevice sync status
Multidevice sync mask
Open
System clock offset
Description
0 = the SYNC_CLK pin is active (default).
1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is
shut down. However, the synchronization circuitry remains active internally to maintain normal
device operation.
0 = DAC reference is enabled (default).
1 = DAC reference is powered down.
See the Synchronizing Multiple AD9959 Devices section for details.
0 = the manual hardware synchronization feature of multiple devices is inactive (default).
1 = the manual hardware synchronization feature of multiple devices is active.
1 = the manual software synchronization feature of multiple devices is active. See the
Synchronizing Multiple AD9959 Devices section for details.
Description
0 = a new delta word is applied to the input, as in normal operation, but not loaded into the
accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the sweep accumulator for one
cycle upon reception of the I/O_UPDATE sequence indicator on all four channels.
0 = the sweep accumulator functions as normal (default).
1 = the sweep accumulator memory elements for all four channels are asynchronously cleared.
0 = a new frequency tuning word is applied to the inputs of the phase accumulator, but not
loaded into the accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the phase accumulator for one
cycle upon receipt of the I/O update sequence indicator on all four channels.
0 = the phase accumulator functions as normal (default).
1 = the phase accumulator memory elements for all four channels are asynchronously cleared.
See the Synchronizing Multiple AD9959 Devices section for more details.
See the Synchronizing Multiple AD9959 Devices section for more details.
See the Synchronizing Multiple AD9959 Devices section for more details.
0 = the manual software synchronization feature of multiple devices is inactive (default).
See the Synchronizing Multiple AD9959 Devices section for more details.
See the Synchronizing Multiple AD9959 Devices section for more details.
Rev. B | Page 40 of 44