ICS1893Y-10LFT IDT, Integrated Device Technology Inc, ICS1893Y-10LFT Datasheet - Page 4

• Manufacturer Part Number: ICS1893Y-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893Y-10LFT

ICS1893Y-10 Rev F 1/20/04
Section
Chapter 7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.4
ICS1893Y-10 Data Sheet - Release
Management Register Set ............................................................................................... 61
Introduction to Management Register Set .............................................................62
Management Register Set Outline .........................................................................62
Management Register Bit Access ..........................................................................63
Management Register Bit Default Values ..............................................................63
Management Register Bit Special Functions .........................................................64
Register 0: Control Register ...................................................................................65
Reset (bit 0.15) ......................................................................................................65
Loopback Enable (bit 0.14) ....................................................................................66
Data Rate Select (bit 0.13) .....................................................................................66
Auto-Negotiation Enable (bit 0.12) .........................................................................66
Low Power Mode (bit 0.11) ....................................................................................67
Isolate (bit 0.10) ......................................................................................................67
Restart Auto-Negotiation (bit 0.9) ..........................................................................67
Duplex Mode (bit 0.8) .............................................................................................68
Collision Test (bit 0.7) ............................................................................................68
IEEE Reserved Bits (bits 0.6:0) .............................................................................68
Register 1: Status Register ....................................................................................69
100Base-T4 (bit 1.15) ............................................................................................69
100Base-TX Full Duplex (bit 1.14) .........................................................................70
100Base-TX Half Duplex (bit 1.13) ........................................................................70
10Base-T Full Duplex (bit 1.12) .............................................................................70
10Base-T Half Duplex (bit 1.11) .............................................................................70
IEEE Reserved Bits (bits 1.10:7) ...........................................................................71
MF Preamble Suppression (bit 1.6) .......................................................................71
Auto-Negotiation Complete (bit 1.5) .......................................................................71
Remote Fault (bit 1.4) ............................................................................................72
Auto-Negotiation Ability (bit 1.3) ............................................................................72
Link Status (bit 1.2) ................................................................................................73
Jabber Detect (bit 1.1) ...........................................................................................73
Extended Capability (bit 1.0) ..................................................................................73
Register 2: PHY Identifier Register ........................................................................74
Copyright © 2004, Integrated Circuit Systems, Inc.
Table of Contents
Title
All rights reserved.
4
Table of Contents
January, 2004
Page