ICS1893Y-10LFT IDT, Integrated Device Technology Inc, ICS1893Y-10LFT Datasheet - Page 96

• Manufacturer Part Number: ICS1893Y-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893Y-10LFT

7.12.10 Auto-Negotiation Complete (bit 17.4)
7.12.11 100Base-TX Signal Detect (bit 17.3)
7.12.12 Jabber Detect (bit 17.2)
7.12.13 Remote Fault (bit 17.1)
7.12.14 Link Status (bit 17.0)
ICS1893Y-10 Rev F 1/20/04
If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
The Auto-Negotiation Complete bit is used to indicate to an STA the completion of the Auto-Negotiation
process. When this bit is set to logic:
•
•
The 100Base-TX Signal Detect bit indicates either the presence or absence of a signal on the Twisted-Pair
Receive pins (TP_RXP and TP_RXN) in 100Base-TX mode. This bit is logic:
•
•
Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has
occurred. This bit is a 10Base-T function.
Bit 17.1 is functionally identical to bit 1.4.
Bit 17.0 is functionally identical to bit 1.2.
Zero, it indicates a Premature End condition has not been detected since either the last read or reset of
this register.
One, it indicates a Premature End condition was detected in the packet since either the last read or reset
of this register.
Zero, it indicates that the auto-negotiation process is either not complete or is disabled by the Control
Register’s Auto-Negotiation Enable bit (bit 0.12)
One, it indicates that the ICS1893Y-10 has completed the auto-negotiation process and that the contents
of Management Registers 4, 5, and 6 are valid.
Zero when no signal is detected on the Twisted-Pair Receive pins.
One when a signal is present on the Twisted-Pair Receive pins.
ICS1893Y-10 Data Sheet - Release
This bit has no definition in 10Base-T mode.
Copyright © 2004, Integrated Circuit Systems, Inc.
and
Section 7.1.4.2, “Latching Low
All rights reserved.
96
Bits”.)
Chapter 7 Management Register Set
January, 2004
Section