ICS1893Y-10LFT IDT, Integrated Device Technology Inc, ICS1893Y-10LFT Datasheet - Page 47

• Manufacturer Part Number: ICS1893Y-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893Y-10LFT

6.3.3 PCS/PMA Transmit Modules
6.3.3.1 PCS Transmit Module
6.3.3.2 PMA Transmit Module
ICS1893Y-10 Rev F 1/20/04
Both the PCS and PMA sublayers have Transmit modules.
The ICS1893Y-10 PCS Transmit module accepts nibbles from the MAC/Repeater Interface and converts
the nibbles into 5-bit ‘code groups’ (referred to here as ‘symbols’). In addition, the PCS Transmit module
performs a parallel-to-serial conversion on the symbols, and subsequently passes the resulting serial bit
stream to the PMA sublayer.
The first 16 nibbles of each MAC/Repeater Frame represent the Frame Preamble. The PCS replaces the
first two nibbles of the Frame Preamble with the Start-of-Stream Delimiter (SSD), that is, the symbols /J/K/.
After receipt of the last Frame nibble, detected when TX_EN = FALSE, the PCS appends to the end of the
Frame an End-of-Stream Delimiter (ESD), that is, the symbols /T/R/. (The ICS1893Y-10 PCS does not alter
any other data included within the Frame.)
The PCS Transmit module also performs collision detection. In compliance with the ISO/IEC specification,
when the transmission and reception of data occur simultaneously and the ICS1893Y-10 is in:
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The ICS1893Y-10 PMA Transmit module accepts a serial bit stream from its PCS and converts the data
into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium
Dependent (TP-PMD) sublayer.
The ICS1893Y-10 PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock
Reference Interface. When the ICS1893Y-10 is configured for an interface that is:
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Note:
1. All of the TXCLK signals are derived from the REF_IN signal that goes to the digital PLL.
2. For the MII, for both the 10Base-T and 100Base-TX modes, the clock that is generated synchronizes
Half-duplex mode, the ICS1893Y-10 asserts the collision detection signal (COL).
Full-duplex mode, COL is always FALSE.
10M MII (that is, 10Base-T), the TXCLK signal is 2.5 MHz
10M Serial Interface, the TXCLK signal is 10 MHz
Either of the following, the TXCLK signal (a buffered version of the REF_IN signal) is 25 MHz:
– 100M MII (that is, 100Base-TX)
– 100M Symbol Interface
ICS1893Y-10 - Release
all data transfers across the MII.
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
47
Chapter 6 Functional Blocks
January, 2004