ICS1893Y-10LFT IDT, Integrated Device Technology Inc, ICS1893Y-10LFT Datasheet - Page 60

• Manufacturer Part Number: ICS1893Y-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893Y-10LFT

6.6.2.7 Management Frame Turnaround
6.6.2.8 Management Frame Data
6.6.2.9 Serial Management Interface Idle State
ICS1893Y-10 Rev F 1/20/04
A valid management frame includes a turn-around field (TA), which is a 2-bit time space between the
REGAD field and the Data field. This time allows an ICS1893Y-10 and an STA to avoid contentions during
read transactions. During an operation that is a:
•
•
A valid management frame includes a 16-bit Data field for exchanging the register contents between the
ICS1893Y-10 and the STA. All Management Registers are 16 bits wide, matching the width of the Data
field. During a transaction that is a:
•
•
If the STA attempts to:
•
•
Note:
The MDIO signal is in an idle state during the time between STA transactions. When the Serial
Management Interface is in the idle state, the ICS1893Y-10 disables (that is, tri-states) its MDIO pin, which
enters a high-impedance state. The ISO/IEC 8802-3 standard requires that an MDIO signal be idle for at
least one bit time between management transactions. However, the ICS1893Y-10 does not have this
limitation and can support a continual bit stream on its MDIO signals.
Read, an ICS1893Y-10 remains in the high-impedance state during the first bit time and subsequently
drives its MDIO pin to logic zero for the second bit time.
Write, an ICS1893Y-10 waits while the STA transmits a logic one, followed by a logic zero on its MDIO
pin.
Read, (OP is 10b) the ICS1893Y-10 obtains the contents of the register identified in the REGAD field and
returns this Data to the STA synchronously with its MDC signal.
Write, (OP is 01b) the ICS1893Y-10 stores the value of the Data field in the register identified in the
REGAD field.
Read from a non-existent ICS1893Y-10 register, the ICS1893Y-10 returns logic one for all bits in the
Data field, FFFFh.
Write to a non-existent ICS1893Y-10 register, the ICS1893Y-10 isolates the Data field of the
management frame from every reaching the registers.
ICS1893Y-10 Data Sheet - Release
The first Data bit transmitted and received is the most-significant bit of a Management Register, bit
X.15.
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
60
Chapter 6 Functional Blocks
January, 2004