PSB3186FV14NT Infineon Technologies, PSB3186FV14NT Datasheet - Page 178

• Manufacturer Part Number: PSB3186FV14NT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Note: Min. value in synchronous state, max. value in non-synchronous state. This
DCL Clock Output Characteristics
Figure 73
Symbol
t
t
t
DCL Clock Input Characteristics
Parameter
Duty cycle
Note: In normal mode the IOM clocks are output only. If the transceiver is disabled
Data Sheet
P
WH
WL
results in a phase shift of FSC when the S-Bus gets activated, this is the FSC
signal is shifted by 135 ns.
(DIS_TR = 1) the IOM clocks become input and e.g. the HDLC controller can still
operate via the IOM-2 interface.
2.3 V
Definition of Clock Period and Width
min.
585
260
260
min.
40
Limit Values
Limit Values
651
325
325
typ.
max.
60
178
max.
717
391
391
Unit
ns
ns
ns
Unit
%
Electrical Characteristics
Test Condition
osc
osc
osc
±
±
±
100 ppm
100 ppm
100 ppm
ISAC-SX TE
PSB 3186
2003-01-30