PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 51

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

ISAC-SX
PEB 3086
Description of Functional Blocks
TE Mode
After multiframe synchronization has been established, the Q data will be inserted at the
upstream (TE ® NT) F
bit position in each 5th S/T frame (see
Table
8).
A
When synchronization is not achieved or lost, each received F
bit is mirrored to the next
A
transmitted F
bit.
A
Multiframe synchronization is achieved after two complete multiframes have been
detected with reference to F
/N bit and M bit positions. Multiframe synchronization is lost
A
if bit errors in F
/N bit or M bit positions have been detected in two consecutive
A
multiframes. The synchronization state is indicated by the MSYN bit in the S/Q-channel
receive register (SQRR1).
The multiframe synchronization can be enabled or disabled by programming the MFEN
bit in the S/Q-channel transmit register (SQXR1).
NT Mode
The transceiver in NT mode starts multiframing if SQXR1.MFEN is set.
After multiframe synchronization has been established in the TE, the Q data will be
inserted at the upstream (TE ® NT) F
bit position by the TE in each 5th S/T frame, the
A
S data will be inserted at the downstream (NT ® TE) S bit position in each S/T frame
(see
Table
8).
Interrupt Handling for Multiframing
To trigger the microcontroller for a multiframe access an interrupt can be generated once
per multiframe (SQW) or if the received S-channels (TE) or Q-channel (NT) have
changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
Data Sheet
51
2003-01-30