PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 92

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.7
The ISAC-SX supports the IOM-2 interface in linecard mode and in terminal mode with
single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD
and DU. The rising edge of FSC indicates the start of an IOM-2 frame. The DCL and the
BCL clock signals synchronize the data transfer on both data lines DU and DD. The DCL
is twice the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the
rising edge of the first DCL clock cycle and sampled at the falling edge of the second
clock cycle.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register.
TE Mode
A DCL signal and BCL signal (pin BCL/SCLK) output is provided and the FSC signal is
generated by the receive DPLL which synchronizes it to the received S/T frame.
The BCL clock together with the two serial data strobe signals (SDS1, SDS2) can be
used to connect time slot oriented standard devices to the IOM-2 interface. If the
transceiver is disabled (TR_CON.DIS_TR) the DCL and FSC pins become input and the
HDLC part can still work via IOM-2. In this case the clock mode bit (IOM_CR.CLKM)
selects between a double clock and a single clock input for DCL.
The clock rate/frequency of the IOM-2 signals in TE mode are:
DD, DU:
FSC (o):
DCL (o):
BCL (o):
Option - Transceiver disabled (DIS_TR = ’1’):
FSC (i):
DCL (i):
LT-S, LT-T, NT, iNT Mode
The IOM-2 clock signals FSC and BCL are input.
In LT-T mode a 1536 kHz output clock synchronous to S is provided at pin SCLK which
can directly be connected to the DCL input. Internal clock dividers provide for generation
of an FSC or BCL output clock at pin FBOUT derived from DCL (see
DD, DU:
FSC (i):
DCL (i):
SCLK (o):
Note: In all modes the direction of the data lines DU and DD is not fix but depending on
Data Sheet
the timeslot which can be seen in the figures below.
IOM-2 Interface
768 kbit/s
8 kHz
1536 kHz (double clock rate)
768 kHz (single clock rate)
8 kHz
1536 ... 4096 kHz, in steps of 512 kHz (double clock rate)
data rate = DCL/2 kbit/s (LT-T mode)
8 kHz
512 ... 4096 kHz, in steps of 512 kHz (double clock rate)
1536 kHz (LT-T mode), BCL derived via DCL/2 (LT-S/NT mode)
92
Description of Functional Blocks
Chapter
PEB 3086
2003-01-30
ISAC-SX
3.4).