PSB21150F-V14 Infineon Technologies, PSB21150F-V14 Datasheet - Page 185

• Manufacturer Part Number: PSB21150F-V14
• Manufacturer: Infineon Technologies

Specifications of PSB21150F-V14

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

IPAC-X
PSB/PSF 21150
Detailed Register Description
TLP ... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming
from the layer 1 controller will not be forwarded to the layer 2 controller.
The setting of TLP is only valid if the IOM interface is active.
4.1.18
CIR0 - Command/Indication Receive 0
Value after reset: F3
H
7
0
CIR0
CODR0
CIC0
CIC1
S/G
BAS
RD (2E)
CODR0 ... C/I Code 0 Receive
Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only
after being the same in two consecutive IOM-frames and the previous code has been
read from CIR0.
CIC0 ... C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is set
only when a new code is detected in two consecutive IOM-frames. It is reset by a read
of CIR0.
CIC1 ... C/I Code 1 Change
A change in the received Command/Indication code in IOM-channel 1 has been
recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by
a read of CIR0.
S/G ... Stop/Go Bit Monitoring
Indicates the availability of the upstream D-channel on the S/T interface.
1: Stop
0: Go
BAS ... Bus Access Status
Indicates the state of the TIC-bus:
0: the IPAC-X itself occupies the D- and C/I-channel
1: another device occupies the D- and C/I-channel
Note: The CODR0 bits are updated every time a new C/I-code is detected in two
consecutive IOM-frames. If several consecutive valid new codes are detected and
Data Sheet
185
2003-01-30