N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 24

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operating features
5.1.10
24/150
When Chip Select (S) is High, the device is deselected, but could remain in the active power
mode until all internal cycles have completed (program, erase, write status register). The
device then goes in to the standby power mode. The device consumption drops to I
Hold (or Reset) condition
The Hold (HOLD) signal is used to pause serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
write status register, program or erase cycle that is currently in progress.
To enter the hold condition, the device must be selected, with Chip Select (S) Low.
The hold condition starts on the falling edge of the Hold (HOLD) signal, provided that the
Serial Clock (C) is Low (as shown in
The hold condition ends on the rising edge of the Hold (HOLD) signal, provided that the
Serial Clock (C) is Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes
Low (this is shown in
During the hold condition, the serial data output (DQ1) is high impedance, and serial data
input (DQ0) and Serial Clock (C) are don’t care.
Normally, the device is kept selected, with Chip Select (S) driven Low for the whole duration
of the hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the hold condition.
Figure 7.
Reset functionality is available instead of Hold in parts with a dedicated part number. See
Section 16: Ordering
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost. On Reset going Low, the device enters
the reset mode and a time of tRHSL is then required before the device can be reselected by
driving Chip Select (S) Low. For the value of tRHSL, see
the lock bits are reset to 0 after a Reset Low pulse.
The Hold/Reset feature is not available when the Hold (Reset) / DQ3 pin is used as I/O
(DQ3 functionality) during Quad Instructions: QOFR, QIOFR,QIFP and QIEFP.
HOLD
C
Hold condition activation
information.
Figure
7).
(standard use)
condition
Hold
Figure
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7).
Table 31.: AC
(non-standard use)
©2010 Micron Technology, Inc. All rights reserved.
condition
Hold
Characteristics. All
N25Q064 - 3 V
AI02029D
CC1
.