N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 94

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Instructions
9.2.9
9.2.10
94/150
DQ0
DQ1
C
S
DQ0
DQ1
*Address bit A23 is “Don’t Care.”
C
S
Figure 52. Program OTP instruction sequence DIO-SPI
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must have been executed
previously.
Apart form parallelizing the instruction code and the address on pins DQ0 and DQ1, the
instruction functionality is the same as the Subsector Erase (SSE) instruction of the
Extended SPI protocol; Refer to
Figure 53. Subsector Erase instruction sequence DIO-SPI
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
Apart form parallelizing the instruction code and the address on the two pins DQ0 and DQ1,
the instruction functionality is the same as the Sector Erase (SE) instruction of the Extended
SPI protocol, please refer to
0
Instruction
1
2
3
23 21 19 17
22 20 18 16
4
0
5
Instruction
6
1
7
2
24-Bit Address
15 13 11 9
14 12 10 8
8
Section 9.1.19: Sector Erase (SE)
3
9 10 11
23 21 19 17
22 20 18 16
Section 9.1.18: Subsector Erase (SSE)
4
5
12 13 14 15
7
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6
5
4
7
3
2
24-Bit Address*
15 13 11
14 12 10
1
0
8
16 17 18 19
7
6
Data Byte 1
9
5
4
10 11
3
2
9
8
1
0
20 21 22 23 24 25 26 27
7
6
12 13 14 15
for further details.
©2010 Micron Technology, Inc. All rights reserved.
7
Data Byte 2
6
5
4
5
4
3
2
3
2
1
0
for further details.
7
1
6
0
Data Byte n
N25Q064 - 3 V
5
4
3
2
1
0