N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 31

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

N25Q064 - 3 V
6.1
Figure 8.
A Flag Status Register (FSR), 8 bits, is also available to check the status of the device,
detecting possible errors or a Program/Erase internal cycle in progress.
Each register can be read and modified by means of dedicated instructions in all the 3
protocols (Extended SPI, DIO-SPI, and QIO-SPI).
Reading time for all registers is comparable; writing time instead is very different: NVCR bits
are set as Flash Cell memory content requiring a longer time to perform internal writing
cycles. See
Legacy SPI Status Register
The Status Register contains a number of status and control bits that can be read or set by
specific instructions: Read Status Register (RDSR) and Write Status Register (WRSR). This
is available in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI).
Table 2.
Status register write protect
SRWD
b7
Register download executed only
during the power on phase
(Non Volatile Configuratio n Register)
Table 31.: AC
Non Volatile and Volatile configuration Register Scheme
Status register format
BP3
NVCR
Characteristics.
Top/bottom bit
(internal Configuration Register)
TB
Device behaviour
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BP2
iCR
Block protect bits
VCR
Co nfiguratio n Register)
and VECR
BP1
Volatile and Non Volatile Registers
Registers download executed after
a WRVCR or WRVECR
instructions, it overwrites NVCR
configurations on iCR
(Volatile Configuration Register)
(Volatile Enhanced
BP0
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WEL
WIP
b0
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