MC145574AAC Freescale Semiconductor, MC145574AAC Datasheet - Page 100

• Manufacturer Part Number: MC145574AAC
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574AAC

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Compliant

11–2
11.2.1
11.2.2
11.2
IDL2 D CHANNEL OPERATION
Gaining Access to the D Channel in the TE Mode
The pins DREQUEST and DGRANT are used in the TE mode of operation to request and grant access
to the D channel. An external device wishing to send a layer 2 frame should bring DREQUEST high,
and maintain it high for the duration of the layer 2 frame. DGRANT is an output signal used to indicate
to an external device that the D channel is clear. Note that the DGRANT signal actually goes high
one received E echo bit prior to the programmed priority class selection. DGRANT goes high at a
count of (n – 1) to accommodate the delay between the input of D channel data via the IDL2 interface
and the line transmission of those bits towards the NT. If at the time of the IDL2 SYNC pulse falling
edge, the DGRANT and the DREQUEST signals are both detected high, the TE mode transceiver
will begin FIFO buffering of the input D channel bits from the IDL2 interface. This FIFO is four bits
deep. Note that DGRANT goes high on the boundaries of the demodulated E bits. In order for the
contention algorithm to work on the D channel, HDLC data must be used. The MC145574 modulates
the D channel data onto the S/T bus in the form that it is received from the IDL2 bus. Thus, the data
must be presented to it in HDLC format. Note that one of the applications of the MC145488 DDLC
is for use with the MC145574 in the terminal mode. The MC145488 performs the HDLC conversion
and D channel handshaking.
Setting the Class for TE Mode of Operation
Recommendation CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specifications mandate two
classes of operation for a TE, with respect to D channel operation. These two classes of operation
are class 1 and class 2. Each of these classes has two associated priorities; high priority and low
priority. These classes and their associated priorities pertain to the number of demodulated E bits
required to be 1, before the D channel is deemed to be clear for use. Using the MC145574 in the
TE mode of operation, the user programs the device for class 1 or class 2 operation by either NR2(0)
or Pin 10.
Table 11–3 illustrates how to configure the MC145574 for either class 1 or class 2 operation. This
table also illustrates when DGRANT will go high. Note that although DGRANT goes high one E bit
before the required count, data will not be modulated onto the D bit timeslots in the S/T frame until
the required number of E bits = 1 are received. Thus, data gets modulated onto the D channel if the
E bit following the low–to–high transition of DGRANT is 1.
The device automatically switches from high to low priority and back, within each class of operation,
in accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605.
Freescale Semiconductor, Inc.
Class 1
Class 2
For More Information On This Product,
Table 11–3. MC145574 Class Operations
Go to: www.freescale.com
NR2(0) = 0
NR2(0) = 1
MC145574
Pin 10 = 0
Pin 10 = 1
and
or
MC145574
DGRANT goes high after seven E bits = 1 in high
priority, and after eight in low priority
DGRANT goes high after nine E bits = 1
in high priority, and after ten in low priority
Required for DGRANT to Go High
Number of E Bits = 1
MOTOROLA