MC145574AAC Freescale Semiconductor, MC145574AAC Datasheet - Page 103

• Manufacturer Part Number: MC145574AAC
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574AAC

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
12.1
12.2
12.3
INTRODUCTION
A layer 1 signalling channel between the NT and TE is provided in the MC145574 in accordance with
CCITT I.430, ETSI ETS 300012, and ANSI T1.605. In the NT and TE direction, this layer 1 channel
is the S channel. In the TE to NT direction, it is the Q channel. The S channel is subdivided into five
subchannels: SC1, SC2, SC3, SC4, and SC5. In normal operation, the NT sets its Fa bit (Bit 14) to
a binary 0 every frame. The “wrapping” action of the TE(s), as outlined in CCITT I.430, ETSI ETS
300012, and ANSI T1.605, causes the Fa bit of the TE(s) to be a 0 also. This is to ensure the existence
of two line code violations per frame, enabling fast synchronization.
Multiframing is activated by the NT by setting the M bit (Bit 26) in the NT and TE frame to a binary
1, once every 20 frames. In addition to this, the Fa bit (Bit 14) in the NT to TE direction is set to a
binary 1, once every five frames. When multiframing is enabled, the NT sends its S channel data
(SC1 through SC5) in the S timeslot (Bit 37) every frame. Table 10–1 shows the order in which the
S channel data is transmitted. Note that the M bit = 1 sets the multiframe boundary. Once every five
frames, the Fa bit is set to 1 in the NT to TE direction. This serves as a Q bit identifier for the TE(s),
who send their Q data in their Fa bit position in the corresponding frames. In order to avoid Q data
collision, those TEs who have not been addressed for multiframing must send 1s in the Q bit timeslots.
ACTIVATION/DETECTION OF MULTIFRAMING IN THE MC145574
Multiframing is initiated by the NT. Detection and compliance with the multiframe structure is mandatory
in the TE(s), and is automatic in the MC145574. BR7(5) is set to 1 to initiate multiframing in an NT–con-
figured MC145574. This causes the M bit to be set to 1 in the next frame. Henceforth, the M, S, and
Fa bits will automatically comply with the structure as outlined in CCITT I.430, ETSI ETS 300012,
and ANSI T1.605. This format is as shown in Table 12–1. When the TE–configured MC145574 has
detected multiframing, it sets NR1(1) (multiframing detect). Henceforth, it automatically complies with
the multiframe format.
WRITING S CHANNEL DATA TO AN NT-CONFIGURED MC145574
Data written to BR2(7:4), BR9(7:4), BR9(3:0), BR10(7:4), and BR10(3:0) is transmitted in subchannels
SC1, SC2, SC3, SC4, and SC5, respectively. The NT–configured MC145574 polls these internal regis-
ters once every 5 ms (a multiframe is 5 ms in duration). If no new data has been written to these
registers, the old data is re–transmitted. When multiframing is disabled, the data in these registers
is ignored and the Fa bit is 0. Note that in the NT mode, these registers come out of reset in the all–0s
state.
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MC145574
MULTIFRAMING
12
12–1