MC145574AAC Freescale Semiconductor, MC145574AAC Datasheet - Page 42

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MC145574AAC

Manufacturer Part Number
MC145574AAC
Description
IC TRANSCEIVER ISDN 32-LQFP
Manufacturer
Freescale Semiconductor
Type
Transceiverr
Datasheet

Specifications of MC145574AAC

Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Package / Case
32-LQFP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Protocol
-
Lead Free Status / Rohs Status
Compliant

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MC145574AAC
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Freescale Semiconductor
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5–4
SCPCLK
SCP Rx
SCPEN
SCP Tx
5.2.4
Figure 5–4. Serial Control Port Byte Register Read Operation Double 8–Bit Transaction
DON’T CARE
SCP Byte Register Write
A byte register write is also a 16–bit SCP transaction. Figure 5–5 illustrates this process. To initiate
an SCP byte register write, the SCPEN must be brought low. As before, the next bit determines whether
the operation is to be read or write. If the first bit is a 0, then a write operation is selected. Again the
next three bits read in from SCP Rx on the subsequent three rising edges of SCPCLK must all be
1 in order to select the pointer nibble register (NR7). The following four bits shifted in are automatically
written into NR7. As in an SCP byte register read, these bits are the address bits for the selected
byte register operation. The next eight rising edges of SCPCLK shift in the data from the SCP Rx.
This data is then stored in the selected byte register. Throughout this operation SCP Tx is in a high–im-
pedance state. Note that if the selected byte is “read only”, then this operation has no effect.
As mentioned previously, an SCP byte access is a 16–bit transaction. This can take place in one 16–bit
exchange or two 8–bit exchanges. If the transaction is performed in two 8–bit exchanges, then SCPEN
should be returned high after the first eight bits have been shifted into the part.
NOTES:
SCPCLK
SCP Rx
SCPEN
SCP Tx
R/W
1. R/W = 1 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.
HIGH IMPEDANCE
DON’T CARE
Figure 5–5. Serial Control Port Byte Register Write Operation
Freescale Semiconductor, Inc.
For More Information On This Product,
R/W
A3
A2
Go to: www.freescale.com
A1
MC145574
A0
A3
A2
A1
A0
HIGH IMPEDANCE
D7
D6
D7 D6
D5
D5
D4
DON’T CARE
D3
D4
D3
D2
D1
D2
D0
D1
D0
MOTOROLA
DON’T CARE
IMPEDANCE
HIGH

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