MC145574AAC Freescale Semiconductor, MC145574AAC Datasheet - Page 72

• Manufacturer Part Number: MC145574AAC
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574AAC

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Compliant

8–4
8.5
transition (low–to–high) has been recognized by the activation/deactivation state machine of the trans-
ceiver. This action indicates that the requested action has been recognized. Note that NR2(3) is a
read/write bit.
NR2(2) — NT: Deactivate Request DR
When NR2(2) is set to 1, a deactivate request input is passed to the activation state machine within
the MC145574 S/T transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and ANSI T1.605.
The deactivate request input is used to initiate deactivation of the transmission loop. Note that this
bit will be returned low by the MC145574 S/T transceiver after its active transition (low–to–high) has
been recognized by the activation/deactivation state machine of the transceiver. This action indicates
that the requested action has been recognized and deactivation is proceeding. Note that NR2(2) is
a read/write bit.
NR2(1) — Activation Timer Expired Input
When NR2(1) is set to 1, an activation timer expired input is passed to the activation state machine
of the MC145574 S/T transceiver. If the transceiver is configured as an NT, this bit corresponds to
the Timer #1 expire input. If the transceiver is configured as a TE, this bit corresponds to the Timer
#3 expire input. These timers correspond to the activation timers outlined in CCITT I.430, ETSI ETS
300012, and ANSI T1.605. The timer expire input informs the activation/deactivation state machine
that sufficient time has elapsed since the request to activate the loop and that attempts to do so should
be abandoned. This bit is normally set by the controlling device and is automatically cleared when
the MC145574 has deactivated the loop. This bit can be reset by hardware or a software reset. Note
that NR2(1) is a read/write bit.
NR2(0) — NT : NT Terminal Class
When the MC145574 is configured for TE mode, this bit sets the class for D channel operation. When
this bit is 0, the chip is set for class 1 operation. Alternatively, when this bit is 1, the chip is configured
for class 2 operation. Class 1 and class 2 operations are as per CCITT I.430, ETSI ETS 300012,
and ANSI T1.605 (i.e., class 1 is the higher class, used for signalling information, and class 2 is the
lower class). The class can also be chosen externally by means of the CLASS/ECHO_IN pin. In this
case, the class is chosen by the logical ‘OR’ of the external pin and NR2(0). NR2(0) can be reset
by a hardware or a software reset. Refer to Section 11 for a detailed description of the D channel.
Note that NR2(0) is a read/write bit.
In the NT Terminal mode, this bit sets the class for D channel operation idle in the TE mode.
NR3
This register is a read/write register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 3 (NR3) follows.
NR3(3) — Change in Rx INFO State IRQ3
The interrupt request condition IRQ3 is generated whenever a change occurs in the received informa-
tion state of the transceiver. In the NT mode, this corresponds to a change in the receiving INFO 0,
NR3
TE: Not Applicable
NT: Timer #1
TE: Timer #3
TE : Class
Change in RX INFO
Freescale Semiconductor, Inc.
For More Information On This Product,
State IRQ3
b3
Go to: www.freescale.com
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MC145574
Multiframe Reception
IRQ2
b2
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TE: D Channel Collision
NT: IRQ6 FECV
Detection
IRQ1
b1
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NT: IRQ7 NT Terminal
D Channel Collision
TE: Not Applicable
MOTOROLA
b0
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