MC145574AAC Freescale Semiconductor, MC145574AAC Datasheet - Page 99

• Manufacturer Part Number: MC145574AAC
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574AAC

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
11.1
INTRODUCTION
The S/T–interface is designed for full–duplex transmission of two 64 kbps B channels and one 16 kbps
D channel between one NT device and one or more TEs. The TEs gain access to the B channels
by sending layer 2 frames to the network over the D channel. CCITT I.430, ETSI ETS 300012, and
ANSI T1.605 specify a D channel access algorithm for TEs to gain access to the D channel. The
MC145574 S/T transceiver is fully compliant with the D channel access algorithm as defined in CCITT
I.430, ETSI ETS 300012, and ANSI T1.605. The D channel operation is handled through the SCP
when using the S/T–interface either in IDL2 or GCI indirect mode, and handled through the C/I channel
when using the S/T–interface GCI direct mode.
The various bits and pins directly pertaining to D channel operation are shown in Tables 11–1 and
11–2.
D channel data is clocked into the MC145574 via D in on the falling edges of DCL. Data is clocked
out onto D out on the rising edges of DCL. For a detailed description of the above pins, refer to Sec-
tion 7. For a detailed description of the above SCP bits, refer to Sections 8 and 9.
SCP Bit
BR13(2)
BR13(7)
OR8(1)
NR2(0)
NR3(0)
NR4(0)
BR7(4)
TQFP Pin 5
TQFP Pin 6
TQFP Pin 7
NT Terminal Class
Interrupt on D Channel
Collision in NT Terminal Mode
Interrupt Enable for NR3(0)
Invert the Echo Channel
Force the Echo Channel to 0
NT1 Star Mode Enable
NT Terminal Mode Enable
Freescale Semiconductor, Inc.
Pin
For More Information On This Product,
NT Mode
SOIC Pin 10
Table 11–2. D Channel Operation
SOIC Pin 8
SOIC Pin 9
Table 11–1. Channel SCP Bit Description
Description
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DGRANT/ANDOUT
DREQUEST/ANDIN
CLASS/ECHO IN
MC145574
IDL2 Mode
D CHANNEL OPERATION
SCP Bit
NR2(0)
NR3(1)
NR4(1)
BR7(1)
BR4(4)
BR7(6)
Class
Interrupt on D Channel Collision
Interrupt Enable for NR3(1)
LAPD Polarity Control
Map Echo Bits to D Timeslots on IDL2 Tx
D Channel Procedures Ignored
Pin Description
GCI_SG/ANDOUT
Tie Low/DREQUEST/ANDIN
Tie Low/CLASS/ECHO IN
TE Mode
Description
GCI Mode
11
11–1