ADV7197KS Analog Devices Inc, ADV7197KS Datasheet - Page 14

• Manufacturer Part Number: ADV7197KS
• Description: IC DAC VID-HDTV 3CH-11BIT 52MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7197KS

• Rohs Status: RoHS non-compliant
• Applications: HDTV
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• Adc/dac Resolution: 11b
• Screening Level: Industrial
• Package Type: MQFP
• Pin Count: 52
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Not Compliant

ADV7197
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Figure 17 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
With these bits it is possible to delay the Y signal with respect to
the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 16 demonstrates this facility.
Color Delay (MR23–MR25)
With theses bits it is possible to delay the color signals with
respect to the falling edge of the horizontal sync signal by up to
four pixel clock cycles. Figure 16 demonstrates this facility.
Reserved (MR26–MR27)
A “0” must be written to these bits.
PrPb DELAY
Y DELAY
NO DELAY
NO DELAY
MAX DELAY
MAX DELAY
ZERO MUST BE
WRITTEN TO
THESE BITS
MR37–MR36
MR27
MR37
TO THESE BITS
BE WRITTEN
MR27–MR26
ZERO MUST
MR26
MR36
MR35
0
1
DAC C CONTROL
Y OUTPUT
PrPb OUTPUTS
MR25
POWER-DOWN
NORMAL
MR35
MR25 MR24 MR23
0
0
0
0
1
MR34
0
1
DAC B CONTROL
0
0
1
1
0
MR24
COLOR DELAY
MR34
POWER-DOWN
NORMAL
0
1
0
1
0
MR33
0
1
MR23
DAC A CONTROL
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)
Figure 18 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Reserved (MR31–MR32)
A “0” must be written to these bits.
DAC A Control (MR33)
Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
DAC B Control (MR34)
Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.
DAC C Control (MR35)
Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
Reserved (MR36–MR37)
A “0” must be written to these bits.
MR33
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
POWER-DOWN
NORMAL
ZERO MUST BE
WRITTEN TO
MR32–MR30
THESE BITS
MR22
MR32
MR22 MR21 MR20
0
0
0
0
1
0
0
1
1
0
MR21
Y DELAY
MR31
0
1
0
1
0
MR20
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
MR30