ADV7197KS Analog Devices Inc, ADV7197KS Datasheet - Page 4

IC DAC VID-HDTV 3CH-11BIT 52MQFP

ADV7197KS

Manufacturer Part Number
ADV7197KS
Description
IC DAC VID-HDTV 3CH-11BIT 52MQFP
Manufacturer
Analog Devices Inc
Type
Video Encoderr
Datasheet

Specifications of ADV7197KS

Rohs Status
RoHS non-compliant
Applications
HDTV
Voltage - Supply, Analog
3.15 V ~ 3.45 V
Mounting Type
Surface Mount
Package / Case
52-MQFP, 52-PQFP
Adc/dac Resolution
11b
Screening Level
Industrial
Package Type
MQFP
Pin Count
52
Voltage - Supply, Digital
-
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADV7197KS
Manufacturer:
AD
Quantity:
20
Part Number:
ADV7197KS
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADV7197–SPECIFICATIONS
5 V DYNAMIC–SPECIFICATIONS
Parameter
Luma Bandwidth
Chroma Bandwidth
Signal-to-Noise Ratio
Chroma/Luma Delay Inequality
Specifications subject to change without notice.
3.3 V DYNAMIC–SPECIFICATIONS
Parameter
Luma Bandwidth
Chroma Bandwidth
Signal-to-Noise Ratio
Chroma/Luma Delay Inequality
Specifications subject to change without notice.
5 V TIMING–SPECIFICATIONS
P
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL AND PIXEL PORT
NOTES
1
2
3
Specifications subject to change without notice.
Guaranteed by characterization.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control: HSYNC/SYNC, VSYNC/TSYNC; DV
arameter
SCLOCK Frequency
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
RESET Low Time
Analog Output Delay
Analog Output Skew
f
t
Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Pipeline Delay
CLK
CLK
1
12
10
5
11
9
2
12
11
2
1
3
8
4
7
6
3
Min
10
0.6
1.3
0.6
0.6
100
0.6
100
5
5
2.0
4.5
7
4.0
(V
to T
AA
(V
to T
MAX
= 4.75 V to 5.25 V, V
AA
(V
T
Min
Min
MAX
MIN
[0 C to 70 C] unless otherwise noted.)
= 4.75 V to 5.25 V, V
AA
Typ
10
0.5
1.5
2.0
16
[0 C to 70 C] unless otherwise noted.)
= 3.15 V to 3.45 V, V
to T
MAX
[0 C to 70 C] unless otherwise noted.)
Max
400
300
300
74.25
81
REF
Typ
13.5
6.75
64
0
Typ
13.5
6.75
64
0
REF
= 1.235 V, R
= 1.235 V, R
REF
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
Clock Cycles
= 1.235 V, R
SET
SET
= 2470
= 2470
Max
Max
SET
= 2470
Conditions
After This Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
HDTV Mode
Async Timing Mode
For 4:4:4 Pixel Input Format
, R
, R
LOAD
LOAD
, R
= 300
LOAD
= 300
Unit
MHz
MHz
dB Luma Ramp Unweighted
ns
Unit
MHz
MHz
dB Luma Ramp Unweighted
ns
= 300
. All specifications T
. All specifications T
. All specifications
MIN
MIN

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