DS33X11+ Maxim Integrated Products, DS33X11+ Datasheet - Page 10

• Manufacturer Part Number: DS33X11+
• Description: IC MAPPING ETHERNET 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X11+

• Applications: Data Transport
• Interface: SPI
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 144-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.
2.1
2.2
2.3
2.3.1
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
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Feature Highlights
General
17mm 256 pin CSBGA Package (DS33X162/X161/X82/X81/X41/W41/W11)
10mm 144 pin CSBGA Package (DS33X11)
1.8V, 2.5V, 3.3V supplies
IEEE 1149.1 JTAG boundary scan
Software access to device ID and silicon revision
Development support includes evaluation kit, driver source code, and reference designs
VCAT/LCAS Link Aggregation (Inverse Multiplexing)
Link aggregation for up to 16 links per ITU-T G.7043/G.7042
Up to 16 members per VCG
4 VCGs for the DS33X162/X82, 2 VCGs for the DS33X42, 1 VCG for the DS33X161/X81/X41/W41
Differential delay compensation for up to 200 ms among members of a VCG
Receive and Transmit are independent (asymmetry support)
User programmable configuration of WAN ports used for VCG
Supports Virtual Concatenation of up to 8 T3/E3 or 16 T1/E1
VCAT/LCAS link aggregation not available in the DS33X11 and DS33W11
HDLC
Up to 4 HDLC Controller Engines
Compatible with polled or interrupt driven environments
Supports Bit stuffing/destuffing without Address/Control/PID fields
Programmable FCS insertion and extraction, with removal of payload FCS
16-bit or 32-bit FCS, with support for FCS error insertion
Programmable frame size limits (Minimum 64 bytes and maximum 2016 bytes)
Selectable self-synchronizing X
Separate valid and invalid frame counters
Programmable inter-frame fill for transmit HDLC
Supports Transparency Processing and Abort Sequence
Programmable frame filtering for FCS errors, aborts, or frame length errors
Bit stuffing with Address/Control/PID/FCS fields
Programmable Interframe fill length.
Transparency processing
Counters: Number of received valid frames and erred frames
Incoming Frame Discard due to FCS error, abort or frame length longer than preset max.
The default maximum frame length is associated with the maximum PDU length of MAC frame
Extract SLARP for external processor interpretation
cHDLC
43
+1 frame scrambling/descrambling
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