DS33X11+ Maxim Integrated Products, DS33X11+ Datasheet - Page 265

• Manufacturer Part Number: DS33X11+
• Description: IC MAPPING ETHERNET 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X11+

• Applications: Data Transport
• Interface: SPI
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 144-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

601h:
Default
10.8 Serial Interface Registers
The Serial Interface contains the Serial transport circuitry and the associated serial port. The Serial Interface
register map consists of registers that are common functions, transmit functions, and receive functions.
Bits that are underlined are read-only; all other bits can be written. All reserved registers and bits with “-“
designation should be written to zero, unless specifically noted in the register definition. When read, the information
from reserved registers and bits designated with “-“ should be discarded.
Counter registers are updated by asserting (low to high transition) the associated performance monitoring update
signal (xxPMU). During the counter register update process, the associated performance monitoring status signal
(xxPMS) is deasserted. The counter register update process consists of loading the counter register with the
current count, resetting the counter, forcing the zero count status indication low for one clock cycle, and then
asserting xxPMS. No events are missed during this update procedure.
A latched bit is set when the associated event occurs, and remains set until it is cleared by reading. Once cleared,
a latched bit will not be set again until the associated event occurs again. Reserved configuration bits and registers
should be written to zero.
10.8.1 Serial Interface Transmit and Common Registers
Serial Interface Transmit Registers are used to control the transmitter associated with each Serial Interface. The
register map is shown in the following Table. Note that throughout this document the HDLC Processor is also
referred to as a “packet processor”.
10.8.2 Serial Interface Transmit Register Bit Descriptions
Register Name:
Register Description:
Register Address:
600h:
Default
Bits 0-15: Line Loopback Enable (LLB[15:0]) Data received on RDATAn will be looped to the Transmit
Serial Port, replacing the data on TDATAn. (Note: TCLKn must be the same clock as RCLKn).
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0 = Line Loopback is Disabled
1 = Line Loopback is Enabled
LLB16
Bit 15
LLB8
Bit 7
0
0
Bit 14
LLB15
LLB7
Bit 6
0
0
LI.LCR1
Serial Interface Loopback Control Register 1
600h
LLB14
Bit 13
LLB6
Bit 5
0
0
LLB13
Bit 12
Bit 4
LLB5
0
0
Bit 11
LLB12
LLB4
Bit 3
0
0
LLB11
Bit 10
LLB3
Bit 2
0
0
LLB10
LLB2
Bit 9
Bit 1
0
0
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LLB9
LLB1
Bit 8
Bit 0
0
0