DS33X11+ Maxim Integrated Products, DS33X11+ Datasheet - Page 50

• Manufacturer Part Number: DS33X11+
• Description: IC MAPPING ETHERNET 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X11+

• Applications: Data Transport
• Interface: SPI
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 144-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.9.3
The starting and ending locations for each queue in DDR SDRAM are user-configured. The address space of a 256
Mbit DDR SDRAM is 24-bits, providing an address range covering 16M 16-bit words. To reduce the complexity of
the user interface, only the upper 10 bits of each start/end queue address are user-configured. This provides a
minimum queue size granularity of 16K 16-bit words, or 32 Kbytes. The 10-bit values programmed into the queue
configuration registers can be multiplied by 32,768 in order to convert to bytes.
Each Serial (WAN) interface has an associated receive WAN Queue in external DDR SDRAM. The WAN Queues
receive data from the WAN interfaces and buffer it for processing. The user configures the size and location of
these queues through control registers in the Arbiter. Starting WAN queue addresses are configured in
AR.WQ1SA-AR.WQ16SA, and ending addresses in AR.WQ1EA-AR.WQ16EA. When using VCAT/LCAS, the
WAN queues are also used for differential delay compensation between members of a VCG. The user-configured
depth of these queues should provide for approximately 200 ms of data at the WAN line rate. This translates to
approximately 10Mb at a 52Mbps rate, and 300kb at 1.544Mbps. While it is possible to configure larger WAN
queues, note that limitations of the VCAT protocol only allow the resolution of 200ms at the line rate, and aliasing
may occur at larger WAN queue depths.
Data from the LAN interface is received into an internal buffer monitored by the SU.LIQOS.LIQOS bits. It is then
immediately processed and placed into one of 16 LAN Queues in external SDRAM, based on the forwarding mode
and information within the frame. Starting WAN queue addresses are configures in AR.LQ1SA-AR.WQ16SA and
ending addresses are configured in AR.LQ1EA-AR.LQ16EA.
The user defines a LAN queue threshold (watermark) that is used to trigger Ethernet flow control or device
interrupts in the AR.LQW register. Because WAN standards do not have a method for interactive flow-control, the
WAN queues do not have user-programmable watermark. The device provides overflow status for the WAN
queues in AR.WQOS and for the LAN queues in AR.LQOS. The device provides an indication that frame
discarding has been triggered due to the level of the WAN queues in AR.WQNFS. The interrupt operation related
to these functions is further defined in Section 8.8.
There are also four special-purpose external SDRAM queues used for frame insertion and extraction. The user
configures the size and location of these through control registers in the Arbiter. The LAN Insert queue is defined
by AR.LIQSA and AR.LIQEA. The LAN Extract Queue is defined by AR.LEQSA and AR.LEQEA. The WAN insert
queue is defined by AR.WIQSA and AR.WIQEA. The WAN Extract queue is defined by AR.WEQSA and
AR.WEQEA. Overflow status for the extraction queues is provided in AR.EQOS
An additional portion of the external SDRAM must be allocated for the Bridge/Filter function when in use. The 4k x
6-byte table used for DA lookup operations will be constructed at the location in the AR.BFTOA register.
The device does not provide error indication if the user creates a connection and queue that overwrites
data for another connection queue. The user must take care in setting the queue sizes.
The LAN and WAN queue pointers must be reset before traffic flow can begin. If this procedure is not followed,
incorrect data may be transmitted. The proper procedure for setting up a connection follows:
Each queue can be individually reset as needed through the starting address register for that queue. All queue
pointers can be reset simultaneously through the AR.MQC register. This register also configures the behavior of
the WAN frame insertion.
Two scheduling algorithms can be used for prioritizing traffic to be transmitted from the LAN queues to the WAN
interface: Strict Priority and Weighted Round-Robin (WRR). WRR scheduling is available only in Forwarding Mode
2, with one Ethernet port. This is configured in the AR.LQSC register.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
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Set up the queue sizes for both LAN and WAN queues.
Set up the LAN Queue threshold and associated interrupt enables if desired.
Reset the pointers for the associated queues
Enable the associated ports.
If a port is disconnected, reset the queue pointer after the disconnection.
Queue Configuration
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