PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 13

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Name
P_IRDY#
P_TRDY#
P_DEVSEL#
P_STOP#
P_LOCK#
P_IDSEL
P_PERR#
P_SERR#
P_REQ#
P_GNT#
P_RESET#
Pin #
AC5
AB5
AA6
AC6
AB6
Y1
AC7
Y7
U3
R2
R3
Page 13 of 112
Type
STS
STS
STS
STS
STS
OD
TS
I
I
I
I
Description
Primary IRDY (Active LOW). Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the primary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated, it
is driven to a de-asserted state for one cycle.
Primary TRDY (Active LOW). Driven by the
target of a transaction to indicate its ability to
complete current data phase on the primary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated,
it is driven to a de-asserted state for one cycle.
Primary Device Select (Active LOW). Asserted
by the target indicating that the device is accepting
the transaction. As a master, bridge waits for the
assertion of this signal within 5 cycles of
P_FRAME# assertion; otherwise, terminate with
master abort. Before tri-stated, it is driven to a
de-asserted state for one cycle.
Primary STOP (Active LOW). Asserted by the
target indicating that the target is requesting the
initiator to stop the current transaction. Before tri-
stated, it is driven to a de-asserted state for one
cycle.
Primary LOCK (Active LOW). Asserted by an
initiator, one clock cycle after the first address phase
of a transaction, attempting to perform an operation
that may take more than one PCI transaction to
complete.
Primary ID Select. Used as a chip select line for
Type 0 configuration access to bridge configuration
space.
Primary Parity Error (Active LOW). Asserted
when a data parity error is detected for data received
on the primary interface. Before being tri-stated, it
is driven to a de-asserted state for one cycle.
Primary System Error (Active LOW). Can be
driven LOW by any device to indicate a system
error condition. Bridge drives this pin on:
This signal requires an external pull-up resistor for
proper operation.
Primary Request (Active LOW): This is asserted
by BRIDGE to indicate that it wants to start a
transaction on the primary bus. Bridge de-asserts
this pin for at least 2 PCI clock cycles before
asserting it again.
Primary Grant (Active LOW): When asserted,
PI7C8154A can access the primary bus. During idle
and P_GNT# asserted, bridge will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
Primary RESET (Active LOW): When
P_RESET# is active, all PCI signals should be
asynchronously tri-stated.
Address parity error
Posted write data parity error on target bus
Secondary S_SERR# asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A