PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 78

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.5
STATUS REGISTER – OFFEST 04h
Bit
5
6
7
8
9
15:10
Bit
19:16
20
21
22
23
24
26:25
Function
VGA Palette
Snoop Enable
Parity Error
Response
Wait Cycle
Control
P_SERR# enable
Fast Back-to-
Back Enable
Reserved
Function
Reserved
Capabilities List
66MHz Capable
Reserved
Fast Back-to-
Back Capable
Data Parity Error
Detected
DEVSEL#
timing
Type
R/W
R/W
R/O
R/W
R/W
R/O
Type
R/O
R/O
R/O
R/O
R/O
R/WC
R/O
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Description
Controls response to VGA compatible palette accesses
0: ignore VGA palette accesses on the primary
1: enable positive decoding response to VGA palette writes on the
primary interface with I/O address bits AD[9:0] equal to 3C6h, 3C8h, and
3C9h (inclusive of ISA alias; AD[15:10] are not decoded and may be any
value)
Controls response to parity errors
0: Bridge may ignore any parity errors that it detects and continue normal
operation
1: Bridge must take its normal action when a parity error is detected
Reset to 0
Controls the ability to perform address / data stepping
0: disable address/data stepping (affects primary and secondary)
Reset to 0
Controls the enable for the P_SERR# pin
0: disable the P_SERR# driver
1: enable the P_SERR# driver
Reset to 0
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the primary interface.
0: no fast back-to-back transactions
1: enable fast back-to-back transactions
Reset to 0
Returns 000000 when read
Description
Reset to 0
Set to 1 to enable support for the capability list (offset 34h is the pointer
to the data structure)
Reset to 1
Set to 1 to enable 66MHz operation on the primary interface
Reset to 1
Reset to 0
Set to 1 to indicate bridge is capable of decoding fast back-to-back
transactions on the primary interface to different targets
Reset to 1
0: No parity error detected on the primary interface (bridge is the primary
bus master)
1: Parity error detected on the primary interface (bridge is the primary
bus master)
Reset to 0
DEVSEL# timing (medium decoding)
01: medium DEVSEL# decoding
Reset to 01
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A