PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 65

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1
7.2
7.2.1
secondary PCI bus, the bridge implements an internal arbiter. This arbiter can be disabled, and an
external arbiter can be used instead. This chapter describes primary and secondary bus arbitration.
PRIMARY PCI BUS ARBITRATION
The bridge implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary
PCI bus arbitration. The bridge asserts P_REQ# when forwarding transactions upstream; that is, it
acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the
queues in the upstream direction, either posted write data or delayed transaction requests, the
bridge keeps P_REQ# asserted. However, if a target retry, target disconnect, or a target abort is
received in response to a transaction initiated by the bridge on the primary PCI bus, the bridge de-
asserts P_REQ# for two PCI clock cycles.
For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been
completely queued. When P_GNT# is asserted LOW by the primary bus arbiter after the bridge
has asserted P_REQ#, PI7C8154A initiates a transaction on the primary bus during the next PCI
clock cycle. When P_GNT# is asserted to PI7C8154A when P_REQ# is not asserted, the bridge
parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is
parked at the bridge and the bridge has a transaction to initiate on the primary bus, the bridge starts
the transaction if P_GNT# was asserted during the previous cycle.
SECONDARY PCI BUS ARBITRATION
The bridge implements an internal secondary PCI bus arbiter. This arbiter supports eight external
masters on the secondary bus in addition to PI7C8154A. The internal arbiter can be disabled, and
an external arbiter can be used instead for secondary bus arbitration.
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied LOW.
PI7C8154A has nine secondary bus request input pins, S_REQ#[8:0], and has nine secondary bus
output grant pins, S_GNT#[8:0], to support external secondary bus masters.
The secondary bus request and grant signals are connected internally to the arbiter and are not
brought out to external pins when S_CFN# is LOW.
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set
taking care of 4 requests / grants. Each set of masters can be assigned to a high priority group and a
low priority group. The low priority group as a whole represents one entry in the high priority
group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions
the highest priority is assigned to the low priority group. Priority rotates evenly among the low
priority group. Therefore, members of the high priority group can be serviced n transactions out of
n+1, while one member of the low priority group is serviced once every n+1 transactions. Figure
7-1 shows an example of an internal arbiter where four masters, including the bridge, are in the
high priority group, and five masters are in the low priority group. Using this example, if all
requests are always asserted, the highest priority rotates among the masters in the following fashion
(high priority members are given in italics, low priority members, in boldface type): B, m0, m1, m2,
m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6 and so on.
Page 65 of 114
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A