PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 68

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1
8.2
GPIO CONTROL REGISTERS
During normal operation, the following device specific configuration registers control the GPIO
interface:
These registers consist of five 4-bit fields:
The bottom four bits of the output enable fields control whether each GPIO signal is input only or
bi-directional. Each signal is controlled independently by a bit in each output enable control field.
If a 1 is written to the write-1-to-set field, the corresponding pin is activated as an output. If a 1 is
written to the write-1-to-clear field, the output driver is tri-stated, and the pin is then input only.
Writing zeroes to these registers has no effect. The reset for these signals is input only.
The input data field is read only and reflects the current value of the GPIO pins. A type 0
configuration read operation to this address is used to obtain the values of these pins. All pins can
be read at any time, whether configured as input only or as bi-directional.
The output data fields also use the write-1-to-set and write-1-to-clear mode. If a 1 is written to the
write-1-to-set field and the pin is enabled as an output, the corresponding GPIO output is driven
HIGH. If a 1 is written to the write-1-to-clear field and the pin is enabled as an output, the
corresponding GPIO output is driven LOW. Writing zeros to these registers has no effect. The
value written to the output register will be driven only when the GPIO signal is configured as bi-
directional. A type 0 configuration write operation is used to program these fields. The rest value
for the output is 0.
SECONDARY CLOCK CONTROL
The PI7C8154A uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data stream.
This data stream is shifted into the secondary clock control register and is used for selectively
disabling secondary clock outputs.
The serial data stream is shifted in as soon as P_RESET# is detected deasserted and the secondary
reset signal, S_RESET#, is detected asserted. The deassertion of S_RESET# is delayed until the
PI7C8154A completes shifting in the clock mask data, which takes 23 clock cycles. After that, the
GPIO pins can be used as general-purpose I/O pins.
An external shift register should be used to load and shift the data. The GPIO pins are used for shift
register control and serial data input. Table 8-1 shows the operation of the GPIO pins.
The GPIO output data register
The GPIO output enable control register
The GPIO input data register
Write-1-to-set output data field
Write-1-to-clear output data field
Write-1-to-set signal output enable control field
Write-1-to-clear signal output enable control field
Input data field
Page 68 of 114
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A