PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 23

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2
2.1
SIGNAL DEFINITIONS
This Chapter offers information about PCI transactions, transaction forwarding across PI7C8154A,
and transaction termination. The PI7C8154A has two 128-byte buffers for read data buffering of
upstream and downstream transactions. Also, PI7C8154A has two 128-byte buffers for write data
buffering of upstream and downstream transactions.
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8154A. Table 2-1 lists the
command code and name of each PCI transaction. The Master and Target columns indicate support
for each transaction when PI7C8154A initiates transactions as a master, on the primary and
secondary buses, and when PI7C8154A responds to transactions as a target, on the primary and
secondary buses.
Table 2-1 PCI TRANSACTIONS
As indicated in Table 2-1, the following PCI commands are not supported by PI7C8154A:
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PI7C8154A never initiates a PCI transaction with a reserved command code and, as a target,
PI7C8154A ignores reserved command codes.
PI7C8154A does not generate interrupt acknowledge transactions. PI7C8154A ignores
interrupt acknowledge transactions as a target.
PI7C8154A does not respond to special cycle transactions. PI7C8154A cannot guarantee
delivery of a special cycle transaction to downstream buses because of the broadcast nature of
the special cycle command and the inability to control the transaction as a target. To generate
special cycle transactions on other PCI buses, either upstream or downstream, Type 1
configuration write must be used.
PI7C8154A neither generates Type 0 configuration transactions on the primary PCI bus nor
responds to Type 0 configuration transactions on the secondary PCI bus.
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
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Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
Responds as Target
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Primary
Y
PCI-to-PCI BRIDGE
Advance Information
Secondary
N
N
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
PI7C8154A