AD9396KSTZ-100 Analog Devices Inc, AD9396KSTZ-100 Datasheet - Page 10

• Manufacturer Part Number: AD9396KSTZ-100
• Description: IC INTERFACE 100MHZ DVI 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9396KSTZ-100

• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9396
Mnemonic
SERIAL PORT
DATA OUTPUTS
DATA CLOCK
POWER SUPPLY
1
The supplies should be sequenced such that V
OUTPUT
DATA ENABLE
CTL(3 to 0)
SDA
SCL
DDCSDA
DDCSCL
MDA
MCL
Red [7:0]
Green [7:0]
Blue [7:0]
DATACK
V
V
(1.8 V to 3.3 V)
PV
DV
GND
DD
D
DD
(3.3 V)
DD
(1.8 V)
(1.8 V)
1
Description
Data Enable that defines valid video. Can be received in the signal or generated by the AD9396.
Control 3, Control 2, Control 1, and Control 0 are output from the DVI stream. Refer to the DVI 1.0 specification for
explanation.
Serial Port Data I/O for Programming AD9396 Registers—I
Serial Port Data Clock for Programming AD9396 Registers.
Serial Port Data I/O for HDCP Communications to Transmitter—I
Serial Port Data Clock for HDCP Communications to Transmitter.
Serial Port Data I/O to EEPROM with HDCP Keys—I
Serial Port Data Clock to EEPROM with HDCP Keys.
Data Output, Red Channel.
Data Output, Green Channel.
Data Output, Blue Channel.
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is different if the
color space converter is used. When the sampling time is changed by adjusting the phase register, the output timing is
shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is
maintained.
Data Clock Output.
This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output
clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2×
frequency pixel clock and a 90° phase shifted pixel clock) and they are produced either by the internal PLL clock
generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted
via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register.
When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all
moved, so the timing relationship among the signals is maintained.
Analog Power Supply.
These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.
Digital Output Power Supply.
A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the V
transferred into the sensitive analog circuitry. If the AD9396 is interfacing with lower voltage logic, V
connected to a lower supply voltage (as low as 1.8 V) for compatibility.
Clock Generator Power Supply.
The most sensitive portion of the AD9396 is the clock generation circuitry. These pins provide power to the clock PLL
and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.
Digital Input Power Supply.
This supplies power to the digital logic.
Ground.
The ground return for all circuitry on-chip. It is recommended that the AD9396 be assembled on a single solid ground
plane, with careful attention to ground current paths.
D
and V
DD
are never less than 300 mV below DV
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2
C Address is 0xA0.
2
DD
C® Address is 0x98.
. At no time should DV
2
C Address is 0x74 or 0x76.
D
pins, so take care to minimize output noise
DD
be more than 300 mV greater than V
DD
may be
D
or V
DD
.