AD9396KSTZ-100 Analog Devices Inc, AD9396KSTZ-100 Datasheet - Page 31

• Manufacturer Part Number: AD9396KSTZ-100
• Description: IC INTERFACE 100MHZ DVI 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9396KSTZ-100

• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x10—Bits[7:2] SOG Comparator Threshold Exit
The exit level for the SOG slicer. Must be > the enter level
(Register 0x0F). The power-up default is 0x10.
0x11—Bit[7] HSYNC Source
0 = HSYNC, 1 = SOG. The power-up default is 0. These
selections are ignored if Register 0x11, Bit 6 = 0.
0x11—Bit[6] HSYNC Source Override
0 = auto HSYNC source, 1 = manual HSYNC source. Manual
HSYNC source is defined in Register 0x11, Bit 7. The power-up
default is 0.
0x11—Bit[5] VSYNC Source
0 = VSYNC, 1 = VSYNC from SOG. The power-up default is 0.
These selections are ignored if Register 0x11, Bit 4 = 0.
0x11—Bit[4] VSYNC Source Override
0 = auto VSYNC source, 1 = manual VSYNC source. Manual
VSYNC source is defined in Register 0x11, Bit 5. The power-up
default is 0.
0x11—Bit[3] Channel Select
0 = Channel 0, 1 = Channel 1. The power-up default is 0. These
selections are ignored if Register 0x11, Bit 2 = 0.
0x11—Bit[2] Channel Select Override
0 = auto channel select, 1 = manual channel select. Manual
channel select is defined in Register 0x11, Bit 3. The power-up
default is 0.
0x11—Bit[1] Interface Select
0 = analog interface, 1 = digital interface. The power-up default
is 0. These selections are ignored if Register 0x11, Bit 0 = 0.
0x11—Bit[0] Interface Select Override
0 = auto interface select, 1 = manual interface select. Manual
interface select is defined in Register 0x11, Bit 1. The power-up
default is 0.
0x12—Bit[7] Input HSYNC Polarity
0 = active low, 1 = active high. The power-up default is 1. These
selections are ignored if Register 10x2, Bit 6 = 0.
0x12—Bit[6] HSYNC Polarity Override
0 = auto HSYNC polarity, 1 = manual HSYNC polarity. Manual
HSYNC polarity is defined in Register 0x11,
Bit 7. The power-up default is 0.
0x12—Bit[5] Input VSYNC Polarity
0 = active low, 1 = active high. The power-up default is 1. These
selections are ignored if Register 0x11,Bit 4 = 0.
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0x12—Bit[4] VSYNC Polarity Override
0 = auto VSYNC polarity, 1 = manual VSYNC polarity. Manual
VSYNC polarity is defined in Register 0x11, Bit 5. The power-
up default is 0.
COAST AND CLAMP CONTROLS
0x12—Bit[3] Input Coast Polarity
0 = active low, 1 = active high. The power-up default
is 1.
0x12—Bit[2] Coast Polarity Override
0 = auto-coast polarity, 1 = manual coast polarity. The power-
up default is 0.
0x12—Bit[1] Coast Source
0 = internal coast, 1 = external coast. The power-up default is 0.
0x12—Bit[0] Filter Coast VSYNC
0 = use raw VSYNC for coast generation, 1 = use filtered
VSYNC for coast generation The power-up default is 1.
0x13—Bits[7:0] Precoast
This register allows the internally generated coast signal to be
applied prior to the VSYNC signal. This is necessary in cases
where pre-equalization pulses are present. The step size for this
control is one HSYNC period. For precoast to work correctly, it
is necessary for the VSYNC filter (0x21, Bit 5) and sync
processing filter (0x21 Bit 7) both to be either enabled or
disabled. The power-up default is 0.
0x14—Bits[7:0] Postcoast
This register allows the internally generated coast signal to be
applied following the VSYNC signal. This is necessary in cases
where postequalization pulses are present. The step size for this
control is one HSYNC period. For postcoast to work correctly,
it is necessary for the VSYNC filter (0x21, Bit 5) and sync
processing filter (0x21, Bit 7) both to be either enabled or
disabled. The power-up default is 0.
STATUS OF DETECTED SIGNALS
0x15—Bit[7] HSYNC0 Detection Bit
Indicates if HSYNC0 is active. This bit is used to indicate when
activity is detected on the HSYNC0 input pin. If HSYNC is held
high or low, activity is not detected. The sync processing block
diagram shows where this function is implemented. 0 =
HSYNC0 not active. 1 = HSYNC0 is active.
0x15—Bit[6] HSYNC1 Detection Bit
Indicates if HSYNC1 is active. This bit is used to indicate when
activity is detected on the HSYNC1 input pin. If HSYNC is held
high or low, activity is not detected. The sync processing block
diagram shows where this function is implemented. 0 =
HSYNC1 not active. 1 = HSYNC1 is active.
AD9396