AD9396KSTZ-100 Analog Devices Inc, AD9396KSTZ-100 Datasheet - Page 18

• Manufacturer Part Number: AD9396KSTZ-100
• Description: IC INTERFACE 100MHZ DVI 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9396KSTZ-100

• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9396
HSYNC Filter and Regenerator
The HSYNC filter is used to eliminate any extraneous pulses
from the HSYNC or SOGIN inputs, outputting a clean, low
jitter signal that is appropriate for mode detection and clock
generation. The HSYNC regenerator is used to re-create a clean,
although not low jitter, HSYNC signal that can be used for
mode detection and counting HSYNCs per VSYNC. The
HSYNC regenerator has a high degree of tolerance to
extraneous and missing pulses on the HSYNC input, but is not
appropriate for use by the PLL in creating the pixel clock
because of jitter.
The HSYNC regenerator runs automatically and requires no
setup to operate. The HSYNC filter requires setting up a filter
window. The filter window sets a periodic window of time
around the regenerated HSYNC leading edge where valid
HSYNCs are allowed to occur. The general idea is that
extraneous pulses on the sync input occur outside of this filter
window and thus are filtered out. To set the filter window
WINDOW
FILTER
VSYNC
HSOUT
HSIN
Figure 10. Sync Processing Filter
Rev. 0 | Page 18 of 48
WINDOW
FILTER
timing, program a value (x) into Register 0x20. The resulting
filter window time is ±x times 25 ns around the regenerated
HSYNC leading edge. Just as for the sync separator threshold
multiplier, allow a ±20% variance in the 25 ns multiplier to
account for all operating conditions (20 ns to 30 ns range).
A second output from the HSYNC filter is a status bit
(Register 0x16[0]) that tells whether extraneous pulses are
present on the incoming sync signal. Extraneous pulses are
often included for copy protection purposes; this status bit can
be used to detect that.
The filtered HSYNC (rather than the raw HSYNC/SOGIN
signal) for pixel clock generation by the PLL is controlled by
Register 0x21[6]. The regenerated HSYNC (rather than the
raw HSYNC/SOGIN signal) for sync processing is controlled by
Register 0x21[7]. Use of the filtered HSYNC and regenerated
HSYNC is recommended. See Figure 10 for an illustration of a
filtered HSYNC.
EXPECTED
EDGE
EQUALIZATION
PULSES