AD9396KSTZ-100 Analog Devices Inc, AD9396KSTZ-100 Datasheet - Page 24

• Manufacturer Part Number: AD9396KSTZ-100
• Description: IC INTERFACE 100MHZ DVI 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9396KSTZ-100

• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9396
Hex
Address
0x21
0x22
0x23
0x24
0x25
Read/Write
or Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[7:0]
[7]
[6]
[5]
[4]
[3]
[2:1]
[0]
[7:6]
[5:4]
[7:0]
Default
Value
1*******
*1******
**0*****
***0****
**** 1***
**** *1**
4
32
1*******
*1******
**1*****
***1****
****1***
*****11*
*******0
01******
**11****
Register Name
SP Sync Filter
Enable
PLL Sync Filter
Enable
VSYNC Filter
Enable
VSYNC Duration
Enable
Auto-Offset
Clamp Mode
Auto-Offset
Clamp Length
VSYNC Duration
HSYNC Duration
HSYNC Output
Polarity
VSYNC Output
Polarity
DE Output
Polarity
Field Output
Polarity
SOG Output
Polarity
SOG Output
Select
Output CLK Invert
Output CLK Select
Output Drive
Strength
Rev. 0 | Page 24 of 48
Description
Enables coast, VSYNC duration, and VSYNC filter to use the
regenerated HSYNC rather than the raw HSYNC.
Enables the PLL to use the filtered HSYNC rather than the raw
HSYNC. This clips any bad HSYNCs, but does not regenerate missing
pulses.
Enables the VSYNC filter. The VSYNC filter gives a predictable
HSYNC/VSYNC timing relationship but clips one HSYNC period off
the leading edge of VSYNC.
Enables the VSYNC duration block. This block can be used if
necessary to restore the duration of a filtered VSYNC.
0 = auto-offset measures code during clamp.
1 = auto-offset measures code (10 or 16) clock cycles after end of
clamp for 6 clock cycles.
Sets delay after end of clamp for auto-offset clamp mode = 1.
0 = delay is 10 clock cycles.
1 = delay is 16 clock cycles.
VSYNC duration.
HSYNC duration. Sets the duration of the output HSYNC in pixel
clocks.
Output HSYNC polarity (both DVI and analog). 0 = active low out.
1 = active high out.
Output VSYNC polarity (both DVI and analog).
0 = active low out.
1 = active high out.
Output DE polarity (both DVI and analog).
0 = active low out.
1 = active high out.
Output field polarity (both DVI and analog).
0 = active low out.
1 = active high out.
Output SOG polarity (analog only).
0 = active low out.
1 = active high out.
Selects signal present on SOG output.
00 = SOG (SOG0 or SOG1).
01 = raw HSYNC (HSYNC0 or HSYNC1).
10 = regenerated sync.
11 = HSYNC to PLL.
0 = don’t invert clock out.
1 = invert clock out.
Selects which clock to use on output pin. 1× CLK is divided down
from TMDS clock input when pixel repetition is in use.
00 = ½× CLK.
01 = 1× CLK.
10 = 2× CLK.
11 = 90° phase 1× CLK.
Sets the drive strength of the outputs.
00 = lowest, 11 = highest.