AD9396KSTZ-100 Analog Devices Inc, AD9396KSTZ-100 Datasheet - Page 34

• Manufacturer Part Number: AD9396KSTZ-100
• Description: IC INTERFACE 100MHZ DVI 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9396KSTZ-100

• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9396
If the VSYNC occurs near the HSYNC edge, this guarantees
that the VSYNC edge follows the HSYNC edge. This performs
filtering also in that it requires a minimum of 64 lines between
VSYNCs. The VSYNC filter cleans up extraneous pulses that
might occur on the VSYNC. This should be enabled whenever
the HSYNC/VSYNC count is used. Setting this bit to 0 disables
the VSYNC filter. Setting this bit to 1 enables the VSYNC filter.
Power-up default is 0.
0x21—Bit[4] VSYNC Duration Enable
This enables the VSYNC duration block which is designed to be
used with the VSYNC filter. Setting the bit to 0 leaves the
VSYNC output duration unchanged; setting the bit to 1 sets the
VSYNC output duration based on Register 0x22. 0 = VSYNC
output duration unchanged. 1 = VSYNC output duration set by
0x22. The power-up default is 0.
0x21—Bit[3] Auto-Offset Clamp Mode
This bit specifies if the auto-offset measurement takes place
during clamp or 10 or 16 clocks afterward. The measurement
takes 6 clock cycles. 0 = auto-offset measurement takes place
during clamp period. 1 = auto-offset measurement is set by
0x21, Bit 2. Default= 1.
0x21—Bit[2] Auto-Offset Clamp Length
This bit sets the delay following the end of the clamp period
for AO measurement. This bit is valid only if Register 0x21,
Bit 3 = 1. 0 = delay is 10 clock cycles. 1 = delay is 16 clock
cycles. Default = 1.
0x22—Bits[7:0] VSYNC Duration
This is used to set the output duration of the VSYNC, and is
designed to be used with the VSYNC filter. This is valid only if
Register 0x21, Bit 4 is set to 1. Power-up default is 4.
0x23—Bits[7:0] HSYNC Duration
An 8-bit register that sets the duration of the HSYNC output
pulse. The leading edge of the HSYNC output is triggered by
the internally generated, phase-adjusted PLL feedback clock.
The AD9396 then counts a number of pixel clocks equal to the
value in this register. This triggers the trailing edge of the
HSYNC output, which is also phase-adjusted. The power-up
default is 32.
0x24—Bit[7] HSYNC Output Polarity
This bit sets the polarity of the HSYNC output. Setting this bit
to 0 sets the HSYNC output to active low. Setting this bit to 1
sets the HSYNC output to active high. Power-up default setting
is 1.
0x24—Bit[6] VSYNC Output Polarity
This bit sets the polarity of the VSYNC output (both DVI and
analog). Setting this bit to 0 sets the VSYNC output to active
low. Setting this bit to 1 sets the VSYNC output to active high.
Power-up default is 1.
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0x24—Bit[5] Display Enable Output Polarity
This bit sets the polarity of the display enable (DE) for both
DVI and analog. 0 = DE output polarity is negative. 1 = DE
output polarity is positive. The power-up default is 1.
0x24—Bit[4] Field Output Polarity
This bit sets the polarity of the field output signal (both DVI
and analog) on Pin 21. 0 = active low out. 1 = active high out.
The power-up default is 1.
0x24—Bit[3] SOG Output Polarity
This bit sets the polarity of the SOGOUT signal (analog only).
0 = active low. 1 = active high. The power-up default setting is 1.
0x24—Bits[2:1] SOG Output Select
These register bits control the output on the SOGOUT pin.
Options are the raw SOG from the slicer (this is the
unprocessed SOG signal produced from the sync slicer), the
raw HSYNC, the regenerated sync from the sync filter, which
can generate missing syncs because of coasting, dropout, or the
filtered sync that excludes extraneous syncs not occurring
within the sync filter window.
Table 15. SOGOUT Polarity Settings
SOGOUT Select
00
01
10
11
The power-up default setting is 11.
0x24—Bit[0] Output Clock Invert
This bit allows inversion of the output clock as specified by
Register 0x25, Bit 7 to Bit 6. 0 = noninverted clock. 1 = inverted
clock. The power-up default setting is 0.
0x25—Bits[7:6] Output Clock Select
These bits select the clock output on the DATACLK pin. They
include 1/2× clock, a 2× clock, a 90° phase shifted clock or the
normal pixel clock. The power-up default setting is 01.
Table 16. Output Clock Select
Select
00
01
10
11
Result
½× pixel clock
1× pixel clock
2× pixel clock
90° phase 1× pixel clock
Function
Raw SOG from sync slicer (SOG0 or SOG1)
Raw HSYNC (HSYNC0 or HSYNC1)
Regenerated sync from sync filter
HSYNC to PLL