AM486DX5-133V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133V16BHC Datasheet - Page 25

• Manufacturer Part Number: AM486DX5-133V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

Step 4 In the next clock, the core system logic deas-
Step 5 The snooping cache starts its write-back of the
Step 6 The write-back access is finished when BLAST
Step 7 In the clock cycle after the final write-back ac-
Step 8 HOLD is sampled by the microprocessor.
ADR
M/IO
CACHE
W/R
ADS
BLAST
BRDY
INV
EADS
HITM
CLK
HOLD
HLDA
Data
Note:
The circled numbers in this figure represent the steps in section 4.8.5.
External
bus master’s
BOFF signal
serts the HOLD signal in response to the
HITM = 0 signal. The core system logic backs
off the current bus master at the same time so
that the microprocessor can access the bus.
HOLD can be reasserted immediately after
ADS is asserted for burst cycles.
modified line by asserting ADS = 0, CACHE = 0,
and W/R = 1. The write access is a burst write.
The number of clock cycles between deassert-
ing HOLD to the snooping cache and first
asserting ADS for the write-back cycles can
vary. In this example, it is one clock cycle, which
is the shortest possible time. Regardless of the
number of clock cycles, the start of the write-
back is seen by ADS going Low.
and BRDY both are 0.
cess, the processor drives HITM back to 1.
1
floating/three-stated
valid
n
2
Enhanced Am486DX Microprocessor Family
3
Figure 9. Write-Back and Pending Access
4
P R E L I M I N A R Y
5
n
n
n+4 n+8 n+12
n+4
Step 9 One cycle after sampling HOLD High, the mi-
Step 10 The core system logic removes hold-off control
Step 11 The bus master restarts the aborted access.
The status of the addressed line is now either shared
(INV = 0) or is changed to invalid (INV = 1).
3.8.5 Write-Back and Pending Access
Scenario : The following occurs when, in addition to the
write-back operation, other bus accesses initiated by
the processor associated with the snooped cache are
pending. The microprocessor gives the write-back ac-
cess priority. This implies that if HOLD is deasserted,
the microprocessor first writes back the modified line
(see Figure 9).
n+8
n+12
croprocessor transitions HLDA transitions to 1,
acknowledging the HOLD request.
to the external bus master. This allows the ex-
ternal bus master to immediately retry the abort-
ed access. ADS is strobed Low, which
generates EADS Low in the same clock cycle.
EADS and INV are applied to the microproces-
sor as before. This starts another snoop cycle.
6
valid
7
8
11
n
9
25
10